ITRS UPDATE

Comparing the defect reduction sections of the most recent versions of the roadmap

David Jensen, AMD; Christopher Long, IBM/Sematech; Robin Worley, Texas Instruments/Sematech; Fred Lakhani, Sematech; and Kenneth W. Tobin, Oak Ridge National Laboratory

The International Technology Roadmap for Semiconductors details the challenges of finding ever-smaller needles in an ever-larger haystack.

The semiconductor industry is constantly refining new technology generations and the plans required to realize them. The 1999 revision of the industry's plan, The International Technology Roadmap for Semiconductors (ITRS), is the result of a yearlong effort to acquire input, debate concepts, and negotiate consensus among various international and domestic working groups on how semiconductor manufacturing technology is likely to progress in the months and years ahead--or at least until the next roadmap revision.¹ The Defect Reduction International Technology Working Group (DR ITWG) received excellent feedback and participation from domestic working groups in Japan, Taiwan, and the United States. It also held informal discussions with yield personnel in Europe and discussed some yield-related topics with Korean representatives from working groups with other thrusts. Input from both high-volume manufacturers of DRAMs and cost-conscious, yet technology aggressive, foundries was considered by the DR ITWG, and much of its work in process was presented in open workshops and industry forums to solicit feedback from interested individuals.

In 1998, MICRO's "Mapping the Roadmap" series provided a detailed review of the defect reduction (DR) sections in the 1997 revision of the roadmap, then known as the National Technology Roadmap for Semiconductors (NTRS).^2­6 This article presents an overview of differences between the DR sections in the 1997 NTRS and the 1999 ITRS. The introductory section also provides a brief review of the major differences between the roadmaps in terms of technology nodes, die sizes, and yield targets. The ITRS is available through Sematech or the SIA, and readers are encouraged to consult it for further details.

Overall Roadmap Technology Characteristics

The major industry indicators that drive the ITRS are shown as overall roadmap technology characteristics (ORTC) in Table I. The table provides annual goals for the key node indicators in the years 1999­2005 and three-year predictions for subsequent years through 2014. Technology requirements also are presented in this way in the ITRS. With the current pace of the industry, the International Roadmap Committee felt that this format was an appropriate way to focus on urgent technology needs in the short term.

Technology Node Indicators	Year of First Product Shipment (Technology Generation)
	1999 (180 nm)	2000	2001	2002 (130 nm)	2003	2004	2005 (100 nm)	2008 (70 nm)	2011 (50 nm)	2014 (35 nm)
DRAM half-pitch (nm)	180	165	150	130	120	110	100	70	50	35
MPU gate length (nm)	140	120	100	85	80	70	65	45	32	22
MPU/ASIC half-pitch (nm)	230	210	180	160	145	130	115	80	55	40
ASIC gate length (nm)	180	165	150	130	120	110	100	70	50	35

Table I: Overall roadmap technology characteristics (ORTC) by technology node.

Technology Nodes. Of greatest importance--and interest--to the industry are the ORTC technology nodes, which define the rates at which critical dimensions will shrink. In the ITRS, DRAM half-pitch and microprocessor unit (MPU) isolated linewidth remain the primary technology node indicators. In the most recent roadmaps, these indicators have both been on a cycle of a 70% reduction every two years. With the 1999 revision, there will be one more two-year cycle for MPU isolated linewidth, while the DRAM half-pitch dimension will be on a three-year cycle. These unsynchronized cycles mean that MPU gate length will lead the DRAM half-pitch by approximately three to four years. In addition, industry benchmarking has shown that the MPU half-pitch typically lags behind the DRAM half pitch by approximately 15%.

Die Size. Another important component of the ORTC is die size and its related dependencies, including litho field size, yield, wafer size, and affordable cost. During the roadmap revision process, various models were used for forecasting the rate of change in die size. These models ranged from the historical rate of doubling die size every two technology nodes (six years) to a model that maintained a constant die size for each phase within a product life cycle. As a result of these modeling activities, it was determined that the desired pace of DRAM product introduction cannot be met with litho and cell-layout-factor (that is, process and design) improvements alone, and that a modest die-size growth (20% every four years) will be necessary. However, significant gaps in technological capabilities must be addressed in order to achieve the forecast cell-layout-factor requirements.

Yield Targets. Finally, international cooperation allowed for DR ITWG to set yield targets based on actual factory performance. Of course, numerous factors will determine individual company targets and results, but the ORTC yield targets for both DRAMs and MPUs were set to accommodate defect budget calculations.

Difficult Challenges

Despite all the yield learning the semiconductor industry has achieved over the past few years, many DR issues identified in the 1997 NTRS as "difficult challenges" remain unchanged. In addition, increased emphasis on ever-smaller defects and on yield loss from systematic mechanisms means that localizing nonvisual defects--previously identified as a challenge for technology nodes beyond 100 nm--is a current difficult challenge. The significant challenges in the >100-nm technology nodes can be categorized as follows:

• Yield Models. Random, systematic, parametric, and memory redundancy models must be developed and validated to correlate process-induced defects, equipment-generated particles, and product and process measures to yield.
  
  
• High-Aspect-Ratio Inspection. High-speed, cost-effective tools must be developed that rapidly detect defects associated with high-aspect-ratio contacts, vias, and trenches and especially defects near or at the bottoms of these
  features.
  
  
• Trace Impurity Specifications. Test structures and advanced modeling are needed to determine the effects of trace impurities on device performance, reliability, and yield.
  
  
• Defect Sourcing. Automated, intelligent analysis and reduction algorithms that correlate facility, design, process, test, and work-in-process (WIP) data must be developed to enable the rapid root-cause analysis of yield-limiting conditions.
  
  
• Nonvisual Defects. Failure analysis tools and techniques are needed to enable the localization of defects where no visual defect is detected.
  
  
• These issues are addressed in the following sections, which discuss the provisions of the ITRS's four DR sections: Yield Model and Defect Budgeting, Defect Detection, Defect Sources and Mechanisms, and Defect Prevention and
  Elimination.

Yield Model and Defect Budgeting

One goal of the roadmaps is to establish process equipment defect budgets based on the corresponding yield targets. The three major differences between the 1997 NTRS and the ITRS in the areas of yield modeling and defect budgeting are described below, followed by a review of the yield model validation methods that were used by the working group.

Changes in Defect Budget Projections. In previous versions of the roadmap, process-induced defect (PID) budget projections were made only for MPUs; the ITRS also includes such projections for DRAMs. In general, the requirements for MPUs are stricter than those for DRAMs because the increasing number of back-end-of-line layers on MPUs makes their production process more complex. Figure 1 shows the defect budget values for a generic metal-etch tool versus time for both DRAMs and MPUs.

Figure 1: ITRS DRAM and MPU defect targets for metal etch by year.

A second change involved the assumptions used in calculating the PID budget targets. In previous roadmaps, PID budget projections were based on the assumption that yield was limited entirely by random defects. In developing the ITRS, assumptions also were made regarding systematic-limited yield targets at specific points in the yield ramp cycle based on discussions with domestic and international manufacturers of both MPUs and DRAMs. The defect budget technology requirement assumptions used in the 1997 and 1999 roadmaps are summarized in Table II.

Budget Category	1997 NTRS	1999 ITRS
Target product	MPU	MPU	DRAM
Yield ramp phase	First year	Ramp phase end	Production phase end
Y0 (%)	60	75	85
YR (%)	60	83	89.5
YS (%)	100	90	95
Cluster parameter	2	5	5
Chip size	340 mm2 in 1999, then increasing	170 mm2 through 2002 then increasing,	132 mm2 in 1999, then increasing

Table II. Defect budget technology requirement assumptions 1997 vs. 1999.

Finally, in the 1997 NTRS, PID budget projections were provided for typical tools within given process zones. In the new roadmap, projections of PID budget values are provided for specific generic tool categories for both MPUs and DRAMs. Table III lists both the 1997 process zone categories and 1999 tool groups, and Figure 2 provides examples of the old and new defect targets for one process area: lithography.

1997 NTRS Process Zone Category	1999 Generic Tool Groups
BEOL interconnect	Metal CVD Metal electroplate Metal etch Metal PVD
BEOL planarization	CMP insulator CMP metal Dielectric track
BEOL surface prep	CMP clean
FEOL doping	Implant high current Implant low/medium current
FEOL interconnect	Plasma etch
FEOL surface prep	Plasma strip Vapor-phase clean Wet bench
FEOL thermal/thin film	CVD insulator CVD oxide mask Furnace CVD Furnace fast ramp Furnace oxide/anneal RTP CVD RTP oxide/anneal
FEOL/BEOL litho	Coat/develop/bake Litho cell Litho stepper
FEOL/BEOL metrology	Inspect PLY Inspect visual Measure CD Measure film Measure overlay Test
FEOL/BEOL wafer handling	Wafer handling

Table III: Defect budget categories: 1997 vs. 1999

Figure 2: Lithography tool defect targets for MPUs: 1997 vs. 1999.

Figure 3: Aspect ratios at future technology nodes identified in the ITRS.

Sematech Defect Budget Validation Study. In general terms, the overall die yield (Y₀) of a semiconductor manufacturing process can be described as the product of a systematic-limited yield component (Y_S) and a random-defect-limited yield component (Y_R). Y_R itself can be described by the negative binomial yield model

where Y_R is a function of the critical area of a device (A), the defect density (D₀), and the cluster factor ().

The defect budget requirements in the ITRS were calculated using this negative binomial model and were based on the results of a 1999 study of current particle-per-wafer-pass and PID levels conducted by Wright Williams & Kelley (Pleasanton, CA) for Sematech. The data were collected at four participating Sematech member companies representing 164 tools, which were divided into 30 distinct generic tool categories.

In order to extrapolate PID budgets to other technology nodes, the researchers took into consideration projected increases in chip size, projected increases in process complexity (as reflected in the number of mask levels), and shrinking feature sizes. The PID extrapolation equation

was used to calculate budget values both forward and backward in technology node from a 150-nm ground-rule process. In the equation, PID is in defects per square meter, F is the average faults per mask level, S is the minimum defect size, and n refers to the technology node. All PID budget values were defined with respect to a critical defect size of 75 nm. This method tends to be a worst-case model, since all process steps are assumed to be at minimum device geometry, where in actuality many processes allow process zones with more relaxed geometries. However, because the same tools are used for both minimum and relaxed geometries, this worst-case model yields relevant results.

For DRAMs, the random fault density used to calculate faults per mask level (for use in the PID extrapolation equation) was based only on the periphery (logic/decoder) area of the chip, which is projected in the ORTC to be 30% of chip area at the stated product maturity level. Because there is no redundancy in the periphery, this portion of the chip must consistently achieve the 89.5% random-defect-limited yield. It was assumed that the core (array) area of a DRAM can implement sufficient redundancy to attain the overall yield target of 85%.

In the future, the periodic validation of random-defect-limited-yield PID budget targets will be required. In addition, methods to model parametric-limited yield, systematic-defect-limited yield, and circuit-limited yield mechanisms should be investigated in order to address those yield loss issues that are usually dominant during the early phases of a yield ramp.

Defect Detection

The future technology requirements for the detection, classification, and review of process related defects are addressed in the defect detection section of the various roadmaps. Generally, those areas identified as challenges in previous versions continue as such in the ITRS.

High-Aspect-Ratio Inspection Capabilities. The 1997 NTRS emphasized the need for high-aspect-ratio inspection tools, and this is again listed as a difficult challenge in the 1999 roadmap. Because aspect ratios as high as 10:1 or 12:1 are projected within the next few technology nodes, as shown in Figure 3, there will be a critical need for a high-speed inspection tool specifically made to look into the bottoms of vias, trenches, and canals for residues and contamination. The existing optical tools used to inspect the surfaces of patterned wafers may find a limited number of defects between metal or poly lines, but there are now no high-throughput tools that can look deep into the grooves of tightly pitched lines and contacts, vias, and similar holes.

Electron-Beam Inspection Tools. Scanning electron microscopy (SEM) tools based on E-beam technology can detect sub-100-nm defects on patterned wafers and are also capable of finding contact or via defects by using voltage-contrast methodologies. However, the analysis process is time-consuming, and only after contacts, trenches, or vias have been filled does voltage contrast work to locate the problem. The analysis process must then be confirmed by reacquiring the defect in a second SEM image and cross-sectioning the suspected opening. Because the corrected die is no longer functional when it has been cut, yield loss becomes an issue. In addition, E-beam-inspected wafers are not routinely returned to the process flow, and questions remain about the effect on ultrathin oxides of the charging necessary for voltage-contrast imaging.

While the ability to find ever-smaller defects is an important defect detection issue, the time required to do so also directly affects the sampling methods that can be used to meet yield targets. A few years ago inspecting an entire cassette of wafers completely was the norm. Today's tool set must go slower to gain the sensitivity required to find the smaller defects. As can be seen in Figure 4, which includes 1994, 1997, and 1998 NTRS goals, the current patterned-wafer inspection tools capable of detecting defects <100 nm are losing the throughput battle. In this regard, E-beam tools can be an excellent means for investigating processes under development but will be of only limited use in in-line inspections.

Figure 4: Throughput vs. minimum detectable defect for current inspection tools.

Automatic Defect Classification. Introduced in the 1997 roadmap, automatic defect classification (ADC) is quickly becoming a de facto requirement for meeting DR goals. Whether it is done on a defect detection or review tool, ADC can separate various defect types or classes with much greater accuracy than human operators. However, current ADC systems are limited in the number of classifications they can effectively analyze, and the generation of the classifiers is time-consuming. The ITRS thus continues to recognize the need for improved classification systems. As the industry moves to smaller and smaller defect sizes, the ability to distinguish between defects becomes increasingly difficult. Tools are needed that can simultaneously detect and differentiate between multiple killer-defect types at high capture rates and throughputs. Advanced ADC systems should also be capable of analyzing defect categories for some level of compositional information. Going even further, the tools should be able to project a potential point of origin for each defect type based on the location of the lot and a given process flow sequence.

Although new tools have been introduced since the 1997 NTRS, they have not addressed the need for high-speed inspection, classification, and characterization of the <100-nm defects that will characterize future technology nodes. Perhaps novel techniques such as acoustics or laser tools that have parallel light sources will provide solutions. In any case, new tools that have both the sensitivity and throughput capabilities required to function as in-line process monitors will be needed.

Defect Sources and Mechanisms

The defect sources and mechanisms (DSM) sections in the various roadmaps provide an overview of the technology requirements for identifying defect sources and investigating the related defect-creation mechanisms. The DSM portion of the ITRS contains several enhancements over the 1997 roadmap.

Integrated Yield Management. To emphasize the impact on yield of visible defects, nondetectable defects, parametric problems, and electrical faults caused by process-induced defects or some interaction between product design, process technology, and product test, the ITRS identifies an integrated approach to yield management as an overarching objective for defect sourcing and yield learning.

Defect-Sourcing Complexity Factor. The fault-isolation complexity factor in the 1997 NTRS has been replaced with a defect-sourcing complexity factor in order to highlight the defect-sourcing challenge. This defect-sourcing complexity factor is defined as the product of the logic transistor density (number per square millimeter), the number of steps in the integrated process flow, and 10⁶. The needle-in-the-haystack challenge facing the industry in terms of this complexity factor is outlined in Figure 5 and Table IV.

Figure 5: The needle-in-the -haystack challenge over various technology nodes. The ratio of haystack to needle increases by 740x from the 180-nm node to the 35-nm node.

 

Budget Category	Year of First Product Shipment (Technology Generation)
	1999 (180 nm)	2002 (130 nm)	2005 (100 nm)	2008 (70 nm)	2011 (50 nm)	2014 (35 nm)
Logic transistor density/mm2 (104)	7	18	41	100	247	609
No. of process steps	380	430	480	530	580	630
Defect sourcing complexity factor (106)	27	76	195	530	1433	3837
Defect sourcing complexity trend (X)	1	3	7	20	54	144

Table IV: The defect-sourceing technology challenge over various technology nodes.

Data Volume. In view of the explosive growth of yield-related data and their importance for yield management, projected data volumes for future technology nodes have been included in the ITRS technology requirements table. Moreover, key findings from a Sematech sponsored 1999 data management system (DMS) assessment study have been included among the roadmap's supplemental materials. Figure 6 presents a summary of the top R&D issues derived from the survey, listed in the order that they should be addressed. (Although the issues at the bottom of the figure will have the greatest effects on DMS technologies, the infrastructure needed to achieve those effects depends on addressing the top issues first.) A sampling of these key areas for R&D investment is reviewed below.

Figure 6: Summary of R&D issues derived from the Sematech DMS survey.

• DMS/WIP Integration. Effective integration of WIP data into data management systems will provide a reliable association of specific process events with process equipment, facilitating the development of advanced tool control concepts.
  
  
• Integration of DMS and IC Design Data. Current data management systems make little or no use of IC design data. Design-for-test and new design strategies could result from a closer integration of these data systems and engineering groups.
  
  
• Event-Driven Data Mining. Data mining is currently done manually and empirically. The ability to initiate data-mining processes based on statistical process control information, context information (for example, from ADC, spatial signature analyses, and wafer tracking), and other process cues would provide automation capability and reduce the dependence on limited human resources.
  
  
• DMS for Advanced Tool/ Process Control. Data management systems are already being used as simple tool controllers (for example, to shut down a tool that is running out of specification), but strategies and methods to provide more advanced capabilities for tool and process control are needed. Indeed, advanced, autonomous DMS tool control is the Holy Grail of yield management.

Defect Sources versus Defect Mechanisms. The ITRS differentiates between defect sourcing and defect mechanisms, defining the former as identifying the point of occurrence of visible or nondetectable defects, parametric problems, or electrical faults. The new roadmap also provides supplemental material on various yield-detracting mechanisms, including process equipment mechanisms, parameter control and process-to-process interaction, design-to-process interaction, and design and process interaction with test.

Yield-Learning Assumptions. For the first time, the 1999 roadmap lists a clear set of yield-learning assumptions. These assumptions include keeping yield ramps at current benchmark levels and sourcing new yield detractors within 50% of theoretical cycle time despite the growing chip complexity, higher data volume, new materials, and novel device
structures.

New Areas of Research. The "potential solutions" table in the ITRS has been expanded from former versions to include such areas of new research as automation methods to correlate design, process, and test; fault-to-defect mapping; design-to-process interaction modeling; process capability analysis; and predictive parametric disturbance modeling.

Defect Prevention and Elimination

Focusing on the cleanliness of process materials and the environment, the defect prevention and elimination (DPE) sections of the roadmaps present technology requirements based on the findings and analyses in other roadmap sections. Changes in the ITRS affect such areas as water and air.

In the 1998 electronic update of the NTRS, state-of-the-art values for TOC levels in deionized (DI) water were included in the DP section for the first time, although it was acknowledged that it is difficult to find yield correlations at such low levels. Additionally, the particle-level requirements for DI water systems were presented in the update as "solutions being pursued" rather than as "no known solutions." These two changes have been carried forward to the 1999 ITRS. In addition, commentary on the need for reduced water consumption has been added.

Another change in the ITRS is that airborne molecular contamination (AMC) requirements have undergone several clarifications. For example, it is explained that because coefficients for organics vary greatly with molecular structure and are also dependent on surface termination, molecular weights <250 amu are not considered detrimental because of their higher volatility. In addition, dopants have been added to the AMC requirements.

The key difficult challenge within the DPE section, however, remains the need for test structures and advanced modeling to determine the effects of trace impurities on device performance, reliability, and yield. Without such correlations, it is very difficult to predict the need for increasing levels of material purity, and without such predictions, semiconductor manufacturers run the risk of not having the right materials and distribution systems available in conjunction with new processes and products. Generally speaking, the lack of a clear correlation between impurities and device performance has led either to a direct relaxation of material impurity requirements or the postponement of possible improvements.

Conclusion

During the interactions among working groups that led to the 1999 ITRS, some themes emerged that seem to sum up the current state of defect reduction efforts. First and foremost, because the systematic component of yield is considered the major yield limiter during early yield ramps, this area must become a key focus of research and development. Addressing these systematic mechanisms through integrated and automatic process control will provide the ability to rapidly optimize process parameters and prevent defect excursions, thus achieving high yields in the early phases of the yield-learning process. And, once high yields are achieved, equipment control must remain paramount to minimize defect excursions in high-volume production.

Although high-speed inspection tools that can detect defects associated with high-aspect-ratio features do not yet exist, this inspection capability will be critical to yield learning and process control in future technology nodes, including in dual-damascene processing. The capture rate of most defect detection tools at high throughputs falls off rapidly at the 130-nm technology node. Bridging this gap will require a significant R&D investment.

The development, advancement, and commercialization of data mining, data management, knowledge discovery, and related tools and techniques will also be critical to the success of integrated yield management and accelerated yield learning. Sourcing nondetectable defects, parametric problems, and electrical faults through a deeper understanding of design-to-process interactions will become just as critical as sourcing visible defects.

Acknowledgments

The authors wish to acknowledge the significant contributions of Mark Camenzind, Darren Dance, Mel Effron, Warren Evans, Bill Fil, Bill Fosnight, Milt Godwin, Rick Jarvis, Toshihiko Osada, Mike Patterson, Vijay Sankaran, Joe Seward, Arye Shapiro, Rebecca Tang, Wanda Tomlinson, and Hank Walker. They would also like to acknowledge additional members of the Defect Reduction Technology Working Group: Edward Akers, Bobby Bell, Rob Cappel, Joe Danko, Derek Fischer, Tony Geller, Remo Kirsch, Madan Kumar, Mark Louis, Jim McAndrew, Mike McIntyre, Tarun Parikh, Earl Prather, Ralph Richardson, Tommy Thomas, Brad VanEck, Penny VanSickle, and Richard Wang.

References

1. The International Technology Roadmap for Semiconductors (San Jose: SIA, 1999).
   
   
2. D Jensen, C Gross, and D Mehta, "New Industry Document Explores Defect Reduction Technology Challenges," MICRO 16, no. 1 (1998): 35­44.
   
   
3. DL Dance, D Jensen, and R Collica, "Developing Yield Modeling and Defect Budgeting for 0.25 µm and Beyond," MICRO 16, no. 3 (1998): 51­61.
   
   
4. C Weber, D Jensen, and ED Hirleman, "What Drives Defect Detection Technology?" MICRO 16, no. 6 (1998): 51­75.
   
   
5. C Gross et al., "Assessing Future Technology Requirements for Rapid Isolation and Sourcing of Faults," MICRO 16, no. 7 (1998): 57­68.
   
   
6. D Jensen and W Fosnight, "Defect Prevention and Elimination: Where the Rubber Hits the Road(map)," MICRO 16, no. 10 (1998): 47­66.

David Jensen is the manager of the wafer fab group world-class supplier program at AMD (Sunnyvale, CA). Until recently he was an AMD assignee at Sematech in Austin, TX, where he served as manager of the defect reduction technology program. Before this assignment his primary responsibility at AMD involved developing and deploying contamination-free manufacturing strategies, a role he also played at Digital Semiconductor in Hudson, MA. Jensen served as cochair of the DR Crosscut Technology Working Group for the 1997 revision of the NTRS and the 1999 revision of the ITRS. Additionally, he was cochair of the 1999 DR ITWG, representing the U.S. region. He has written and presented many papers on contamination control and defect reduction technology and is a member of MICRO's editorial advisory board. He holds a BS in mechanical engineering from Arizona State University in Tempe. (Jensen can be reached at 512/602-6730 or david.jensen@amd.com.)

Christopher Long is a Sematech assignee from IBM working as a project manager in the yield management tools program. Before joining the consortium, his primary responsibility as a member of IBM's technical staff was yield characterization of 16­64-Mb DRAM products. Long has published and presented several papers on yield modeling and defect reduction technology. He holds a BS in physics from Beloit College in Beloit, WI, and an MS in engineering from the Thayer School of Engineering, Dartmouth College, in Hanover, NH. (Long can be reached at 512/356-3916 or chris.long@sematech.org.)

Robin Worley is the project manager for advanced defect detection at Sematech. He is an assignee from Texas Instruments, where he was section head for yield enhancement of logic circuits in the DP-1 facility. Worley has worked in yield enhancement for about 10 years and served as cochair of the domestic working group for the ITRS. He has also worked at ASM America as a CVD process development engineer in the R&D applications lab. He has a BS in electrical engineering technology from Texas Tech University in Lubbock. (Worley can be reached at 512/356-3946 or robin.worley@sematech.org.)

Fred Lakhani is a program mentor for the yield management tools organization at Sematech and leads projects in computer-aided fault-to-defect mapping and automated image retrieval. He has held many engineering and management positions in device characterization and yield management and has published numerous articles in these fields. Lakhani served as cochair of the working group on the defect sources and mechanisms portion of the DR section of the ITRS. He has a BSEE from the University of Texas in Arlington and an MSEE in materials and devices from Southern Methodist University in Dallas. He is also a graduate of the Institute of Managerial Leadership at the University of Texas in Austin. (Lakhani can be reached at 512/356-7011 or fred.lakhani@sematech.org)

Kenneth W. Tobin, PhD, leads the image science and machine vision group at the Oak Ridge National Laboratory (Oak Ridge, TN). His technical research includes scene analysis and pattern recognition for machine vision as applied to industrial real-time, high-speed inspection and automation problems. He has authored or coauthored more than 76 technical publications in the areas of nondestructive testing and analysis, signal and image processing, and pattern recognition. He holds three U.S. patents, with three additional patents pending, in the areas of computer vision and photonics. Tobin has conducted research on rapid yield learning with the semiconductor industry since 1992, including studies on image defect classification, wafer-map spatial signature analysis, and content-based image retrieval. He has a BS in physics and an MS in nuclear engineering from Virginia Tech in Blacksburg and a PhD in nuclear engineering from the University of Virginia in Charlottesville. (Tobin can be reached at 865/574-8521 or tobinkwjr@ornl.gov)

MicroHome | Search | Current Issue | MicroArchives
Buyers Guide | Media Kit