Process Equipment Control

Controlling defectivity in advanced silicon etch systems

Brett Richardson, Lam Research

A change in chamber materials and the use of an in situ dry clean process can improve the uptime and productivity of etch tools.

The control of both metallic and particulate contamination during wafer processing has become increasingly critical as device geometries have continued to shrink. Minimizing contaminant levels in high-density polysilicon etch chambers is particularly important because the gate oxide is exposed during processing. Ultrathin gate dielectrics, which are extremely susceptible to contamination-induced gate leakage and threshold-voltage shifts, are a particular concern. Particulate contamination also can lead to the formation of shorts and interfere with subsequent deposition or etch steps. In addition, because shallow trench isolation requires etching directly into the silicon substrate to increase packing density, the entire area of each transistor is vulnerable to contamination. Any contaminants introduced during the etch process can migrate quickly through the transistors' working areas, causing device failures that decrease yields.

Contamination can be introduced into an etch chamber during both the plasma process cycle and chamber cleans. Therefore, in its research into ways to minimize contaminants in silicon etch systems, Lam Research (Fremont, CA) has taken a total systems approach that has included eliminating contaminant sources in the chamber as well as managing contamination levels through in situ cleans. The measures subsequently implemented have not only protected device yields, but also improved system uptime and overall productivity. This article discusses the investigation of those contamination control methods and the benefits realized by the wafer fabs that participated in the studies.

Eliminating Contamination Sources

Metallic contamination requirements for silicon etch tools have fallen to <5 x 10¹⁰ atoms/cm², which makes the choice of construction materials for etch systems a significant concern. The etch chamber, including windows, vacuum fittings, spacers, and liners, can be a potential source of contamination if any component containing undesirable impurities reacts with the chlorine- and fluorine-based chemistry. Chamber surfaces near powered electrodes that receive ion bombardment or those in direct contact with the reactive plasma are especially prone to contaminant generation. For example, the edge ring used to protect the lower electrode is subject to some ion bombardment and has a limited etch or sputter rate. Thus, the by-products from plasma reacting with this ring may be a significant source of metallic contaminants.

To address this issue, an alumina ceramic edge ring used in several silicon etch systems was studied to determine its role in contributing to contamination. This ring was the only ceramic material in the TCP 9400-series chambers exposed directly to plasma. Alumina ceramics are commonly used in etch chambers where durable insulating materials are required because the erosion rate of alumina is very low, even when it is subjected to energetic ion bombardment. Although such ceramics are durable, they do contain a number of metallic impurities. Therefore, a quartz replacement ring, with significantly lower impurity levels, was also investigated to determine if its use would lower contaminant levels in the process chamber. Table I compares the metallic impurity levels of two typical alumina ceramics with quartz. In addition to the metallic impurities listed, the quartz has an aluminum level by weight of only 8 ppm, while aluminum is a principal component of alumina (Al^₂O^₃).

 

Material Impurity (ppm by weight) Fe Mg Ca Na K Quartz (GE-144) 0.2 <0.1 0.4 0.7 0.6 Ceramic, 99.5% alumina 230 660 7800 260 80 Ceramic, 99.9% alumina 10 NAa NAa 20 NAa aBelow the limits of detection, insignificant.

Table I: Comparison of metallic impurities in ceramic and quartz.

Metallic contamination levels on test wafers were measured after they had been exposed to various silicon etch process conditions in chambers that had either a quartz or a ceramic edge ring. Secondary ion mass spectroscopy (SIMS) was used to measure aluminum, while the levels of potassium (K), titanium (Ti), chromium (Cr), manganese (Mn), copper (Cu), calcium (Ca), zinc (Zn), iron (Fe), and nickel (Ni) were determined using total x-ray fluorescence (TXRF). Selected results for both the test wafers and an unprocessed control wafer are shown in Table II.

 

Etch System Process Impurity on uartz Edge Ring (1010 atoms/cm2) Impurity on Ceramic Edge Ring (1010 atoms/cm2) Al Fe Ni Al Fe Ni Tool A Poly main etch 3.7 4.7 3.3 160 16.7 2.3 Tool A Poly overetch – 3.7 2 – 27.6 7.3 Tool B Poly main etch – 5 <11 – 37 <9 Tool C Gate stack etch 4.2 – – 15 – – Control Wafer No process 0.35 0.8–3.5 <1 0.35 0.8–3.5 <1

Table II: Contamination comparison between quartz and ceramic edge rings. (Dashes indicate that data were not collected.)

A comparison of the measurements for the two types of rings shows that aluminum contamination was significantly lower with the quartz edge ring, particularly following a process with a relatively high direct-current bias such as poly main etch, where more etching of the edge ring would be expected. Indeed, with the quartz edge ring, aluminum contamination was <5 x 10¹⁰ atoms/cm² for all process conditions tested. The high level of contamination with the ceramic edge ring is not surprising, since the material is >99.5% Al_²O_³.

For potassium, titanium, chromium, manganese, and copper, metal contamination was below the detection limits for TXRF on the control and on the test wafers processed in chambers with quartz or ceramic edge rings. Calcium and zinc were found on the control wafer but were not detected on samples after etch processing. The levels of both iron and nickel increased after etching in chambers with either ring material, but iron contamination remained at or below 5 x 10¹⁰ atoms/cm² only when the quartz edge ring was used. The iron levels with the ceramic edge rings were significantly higher because the iron impurity level in the ceramic is 230 ppm compared with 0.2 ppm in the quartz. In sum, metallic contaminant levels were lowered by substituting a quartz edge ring for a ceramic one.

In addition to reducing metal contamination on the wafer, a secondary benefit of using the quartz edge ring was that it helped reduce etch defects. Energy-dispersive x-ray (EDX) analysis of particles that caused etch defects on wafers processed in chambers with a ceramic edge ring consistently identified aluminum as a component of the particles. Moreover, when samples of the etch by-products deposited in a chamber with a ceramic edge ring and a chamber with a quartz edge ring were collected and analyzed by EDX, aluminum was found to be a component of the residue taken from the former but not the latter chamber. Figure 1 details the etch by-products from a chamber with a ceramic edge ring.

 

Figure 1: EDX analysis of deposited etch by-products from a chamber with a ceramic edge ring.

At one wafer fab participating in this study, defectivity levels on product wafers were reduced by more than 50% after a quartz edge ring was installed in its existing etch system, as shown in Figure 2. The reduced defectivity levels can be attributed in part to the better adhesion of etch by-products to the chamber walls that occurs when the metal contamination levels of such residues are reduced. Additionally, in situ plasma cleans more effectively remove the chamber deposits when metal contamination generated by ceramic rings is eliminated from the deposition. These test results show that it is advisable to replace ceramic rings with quartz rings in etch tools to reduce metal contamination and defectivity levels.

Managing Contamination Using In Situ Chamber Cleans

Polysilicon, polycide, and silicon etch processes produce etch by-products that may contain carbon, silicon, silicon oxides, and nitrides as well as chlorides, bromides, and fluorides from the etch chemistries. Over time, these by-products accumulate on the chamber walls and may eventually flake off, generating particle contamination. Additionally, as residues build up in the chamber, the deposits begin to participate in the etch process in ways that can affect the etch rate, etch profile, critical-dimension control, and remaining oxide. To prevent such occurrences, etch systems must be periodically shut down for scheduled--and sometimes unscheduled--chamber wet cleans.

 

Figure 2: Defectivity comparison of product wafers processed in chambers with a ceramic or quartz edge ring.

A wet clean involves opening the chamber for manual removal of deposited etch by-products and also may include replacing chamber parts. The cleaned system must then undergo a requalification to test vacuum integrity, particulate levels, and etch results. The chamber may need to be conditioned by running the etch process with dummy wafers until stable etch results are achieved. The etch system is, of course, unavailable for production use during the wet clean and requalification period. Wet cleans thus reduce system availability, lower productivity, and add the cost of dummy wafers to production expenses, all of which increase the system cost of ownership.

The time between wet cleans, measured either by the number of wafers processed or as cumulative etch time, can be extended if the chamber can be cleaned by an in situ dry clean process. The maximum benefit from such cleans is realized when the cleaning process can be run in an automated mode without a wafer in the chamber (a dummy wafer would prevent effective cleaning of the wafer chuck) and when dummy wafers are not required for subsequent chamber conditioning. The dry clean chemistry used may consist of a combination of fluorine, chlorine, and oxygen gases. Fluorine-containing gases are very effective at removing silicon-based residues and will also clean silicon oxides. Oxygen cleans off organic by-products of the photoresist that were removed during the etching process, and chlorine aids in the removal of certain silicide etch by-products.

Following the dry clean, a waferless recovery step may need to be run to remove residual fluorine from the chamber and recondition the chamber walls. It is important that all chamber materials are compatible with the dry clean chemistry so that the cleaning process will not generate additional contaminants. Before hardware components are chosen for a chamber, the trade-off between consumables lifetimes, metallic contamination, and chemistry compatibility must be considered.

The use of a waferless plasma dry clean and conditioning process was investigated in TCP 9400PTX etch systems with a ceramic-free chamber and wafer chuck. The process was automated by specifying it in the system's wafer-flow recipe, which allowed the plasma cleaning and recovery process to be tailored to each product type being etched. In addition, the cleaning frequency could be customized for optimal results. It was found that implementing the waferless autoclean system (WAC) with a waferless recovery step (WRS) in ceramic-free chambers offers several advantages:

• Reduced particle excursions between wet cleans.
• Increased mean time between wet cleans (MTBC).
• Reduced wet clean time. (Because there was less deposited residue to remove from the ceramic-free chambers than from ones containing ceramics, fewer pump/purge cycles were required before chamber venting.)
• Reduced chamber conditioning time.
• Reduced dummy wafer consumption for chamber conditioning.
• Improved process repeatability, especially for mixed-product etching.

These benefits contribute to significant cost savings by improving system uptime and reducing the costs of consumables and ownership. The wafer fabs participating in the study also reported improvements in etch rate stability, as demonstrated in Figure 3. Table III summarizes the productivity improvements that were achieved at four wafer fab sites that implemented the waferless cleaning process.

Conclusion

By taking a total systems approach, participants in a research project on contamination control measures have realized significant improvements in etch system productivity. Specifically, the risk of wafer exposure to metallic contamination during critical silicon etching was significantly reduced by eliminating exposed ceramic parts in the process chamber. The elimination of ceramics also resulted in improved product defectivity performance between wet clean cycles.

 

Figure 3: Comparison of polysilicon etch rate repeatability before and after a waferless autoclean was implemented. (Data courtesy of Cypress Semiconductor, San Jose.)

In addition, an in situ dry clean process was developed that extended the MTBC. This plasma clean method was found to be more effective after metallic contamination sources were eliminated. Tests at several fabs using a variety of silicon etch processes verified that improvements in particle control and etch rate stability were achieved using waferless autocleans in ceramic-free chambers. At all test sites, the risks from both metallic and particulate contamination were reduced, equipment utilization was improved, and the cost of ownership for the etch system decreased.

Acknowledgments

The author wishes to acknowledge the contributions of Wendy Nguyen and Chris Vetter of Lam Research, and Usha Raghuram of Cypress Semiconductor (San Jose), who supplied some of the data presented in this article.

Brett Richardson is a senior staff process engineer at Lam Research (Fremont, CA), where he has worked since 1992. He has 16 years of experience in plasma etch process development and reactor design. Richardson holds seven patents in the areas of particle and system control and has published many journal articles. He received a BS in mathematics from David Lipscomb College in Nashville, TN, and an MS in physical chemistry from the Georgia Institute of Technology in Atlanta. (Richardson can be reached at 510/659-0200 or brett.richardson@lamrc.com.)

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