INDUSTRY NEWS

ROUND THE CIRCUIT

Sematech starts low-k look

International Sematech has completed first-phase evaluations of low-k dielectric films for processing advanced interconnect structures in devices with sub-0.18-µm linewidths. During the preliminary phase the consortium made one-level copper damascene test structures. The films used to fabricate the structures have a dielectric constant in the range of 3.0 to 2.1. The evaluation is intended to help member companies identify methods for successfully integrating low-k materials in their manuufacturing lines. Input from the member firms, suppliers, university researchers, and national laboratories determined the scope and evaluation methods for measuring the physical, electrical, and thermomechanical properties of the materials.

Ten suppliers provided the materials used in making the devices: Applied Materials, Asahi Chemical, Dow Chemical, Dow Corning, Hitachi Chemical, Honeywell Electronic Materials, JSR, Novellus, Battelle PNNL, and Schumacher. Among the tools used to make the devices were low-k spin systems and curing tools from TEL; etch and strip tools from Lam, Applied, Eaton, and TEL; copper deposition gear from Novellus and Semitool; and CVD dielectric deposition systems from Novellus and Applied. CMP systems were supplied by Applied and SpeedFam-IPEC.

Paul Winebarger, International Sematech's director of interconnect, calls the evaluation "a learning and data gathering process." The consortium will next test new materials with the lower dielectric constants needed to make post-0.18-µm generation devices. Winebarger says the program focuses on critical issues such as "extensive material characterization, process integration, and electrical performance." Materials used successfully in making the one-level structures will be used to make via chain structures with two levels of copper metal in low-k dielectric materials, he adds. (See the lead story on page 14 of this month's issue for more developments on the low-k dielectrics front.)

Mask research yields results

A mask-coating technology that keeps photoresist and contaminants from sticking to the mask during contact printing has been developed by Motorola Labs. Called Super Clean Mask coating, the technology has been made available by Motorola and EV Group (EVG), a manufacturer of wafer bonders, mask aligners, and coating systems. The coating technique extends mask-cleaning cycles without degrading the feature size resolution, thus increasing yields, the two companies assert. It was designed specifically for making devices requiring contact printing. The products include MEMS, microwave transistors, Schottky diodes, and solar cells. An increase in contact printing has been driven by MEMS, laser, and compound semiconductor products using 3- to 8-in. wafers, according to Motorola. Information: 602/437-9492.

NIST offers lean help

A new partnership between the National Institute of Standards and Technology (NIST) and a private firm is aimed at helping small manufacturers run their plants more efficiently. NIST's Manufacturing Extension Partnership (MEP) network has signed an agreement with Productivity to offer the company's 5-S visual systems course covering so-called lean manufacturing concepts. The course had been available only to large manufacturers. NIST is making it possible for small businesses to take the program through MEP.

MEP field manufacturing specialists trained by Productivity will use customized materials to teach the 5-S visual systems course, NIST says. The course teaches plant managers the "five pillars" of workplace organization and standardization: sort, set in order, shine, standardize, and sustain. Managers will learn how to map a current situation, create an optimal condition, and maintain it using visual controls. The program teaches employees how to work more efficiently and safely. It is also designed to make work more satisfying and productive, NIST says. The lean manufacturing concept began in Japan in the 1970s as a way of eliminating work activities that added no real value to a product or service, according to the government institute. Information: 1/800/MEP-4MFG; http://www.mep.nist.gov.

RTP breakthrough claimed

A new annealing technology for rapid thermal processing technology will handle ultrashallow junctions in chips with 0.10-µm geometries, the technique's developer claims. Vortek Industries of Vancouver, BC, Canada, says its Impluse anneal RTP technology offers exceptional control for thermal processing because it uses the company's proprietary arc-lamp RTP system while other tools use an array of tungsten-halogen lamps, reflective chambers, and wafer rotation. The method combines very rapid thermal ramp-up and cooldown because of the system's absorbing chamber design, Vortek says. System throughput is 120 wafers per hour.

"The new system will provide unprecedented performance for the spike anneal of ultrashallow source and drain junctions," says Reg Allen, company president. "It will break the barrier facing current RTP technologies." The Impluse system will be in beta-site tests within the next 18 months, according to the company.

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