Surface Chemistries

Optimizing wafer rinsing processes to conserve DI water

Ron Chiarello, Stanford University; Russ Parker, Agilent Technologies; and Mike Tritapoe, Advanced Micro Devices

Used with the standard RCA clean, two alternative rinse processes can provide improvements in tool performance, generate cost savings, and benefit the environment.

As the increasing demand for high-performance integrated circuits has led to more-complex device architectures, high packing densities, large die sizes, and larger wafers, there has been an accompanying need for larger volumes of chemicals and deionized (DI) water for use in the cleaning and other surface preparation steps that are critical to the semiconductor manufacturing process flow. These cleaning and rinsing steps are required to provide the necessary wafer surface quality and to isolate each process step from the others. In some fabs the DI water used for rinsing during front-end-of-line (FEOL) surface preparation (through the first contact cut) and back-end-of-line processing can total 20 million gallons or more per month. The cost of obtaining water, the construction and maintenance of large-scale deionization plants, and the treatment and disposal of wastewater can add significantly to overall manufacturing costs. Some cost-of-ownership models show that the relative cost of DI water for processing 300-mm wafers will almost triple compared with other factors.¹ In addition, the construction of new manufacturing sites around the world requires that an environmentally correct approach be taken from the outset. A transparent answer to all of these challenges is to reduce water consumption, thereby lowering both fixed and operating costs as well as putting less strain on natural resources.^2­5

One approach to reducing DI-water use is to implement recycling and reclaim procedures. In recycling, water used in a particular process is reprocessed and reused in the same or similar processes. Doing this requires water collection, storage, testing, and conditioning in some parts of the overall DI-water system. In reclaim, used water is reused in some other part of the fab where lower water quality is acceptable (e.g., in cooling towers and scrubbers). Recycling requires an investment in large, complex facilities to provide significant quantities of reusable water. Furthermore, both recycling and reclaim are facilities-level techniques and thus do not offer any tool and process-enhancement benefits.

This article focuses on an approach to reducing DI-water use that significantly differs from but complements the recycling/reclaim strategy: the redesign of aqueous rinsing processes to use less water and to improve the overall process flow. In addition to reducing DI-water consumption, the development of optimized rinse processes provides other benefits, including shorter process times, higher tool utilization, and higher throughputs—all of which lead to a lower cost of ownership.

The optimization of rinse processes must be based on detailed information about DI-water use at the tool, the type and concentration of waste stream contaminants, and wafer surface contamination and defects. Process and equipment engineers use this cross-functional information to determine the optimum rinse time, water volume, flow-rate programming, temperature, and excitation (such as megasonic energy). The information provides engineers with the knowledge needed to decide between a set of discrete choices which can be justified based on gains in cost savings and cost avoidance, tool performance, and the environmental benefits of reduced water and energy consumption. Implementation of this approach in FEOL surface preparation at several fabs has led to DI-water savings of 25­70%, rinse time reductions of 25­60%, and annual cost savings and cost avoidance of from $250,000 to more than $2 million per fab.

Types of Rinse Processes

The standard RCA clean and its variations commonly used in FEOL processing fulfill all of the requirements for the cleaning and preparation of wafer surfaces. They effectively remove all types of surface contaminants; cause no damage to the silicon or silicon dioxide (SiO^₂) surfaces; are simple, safe, and economical to use in production facilities; and use and create materials and waste that are environmentally benign. Figure 1 shows the path wafers follow in a typical RCA clean. The initial sulfuric acid/hydrogen peroxide mix (SPM) step removes gross organics and photoresist; standard clean 1 (SC-1), consisting of ammonium hydroxide/hydrogen peroxide, removes particles and organic contaminants; the hydrofluoric acid (HF) step etches SiO^₂; and standard clean 2 (SC-2), consisting of hydrogen chloride/hydrogen peroxide, removes metal contaminants that may result from the previous process steps. Each of these cleaning steps is followed by a DI-water rinse process (including the final rinse, or FR, step).

Figure 1: typical RCA cleaning process flow, with overflow rinse (OR) or overflow dump rinse (ODR) steps between each chemical treatment.

Figure 2 illustrates the types of rinse processes that can be used in the RCA clean. An overflow rinse (OR) usually follows an etching chemistry (HF or buffered oxide) and involves overflowing the rinse tank at a DI-water flow rate of 20­40 L/min for 8 to 10 minutes. A quick dump rinse (QDR) is performed by filling the rinse tank with DI water to cover the wafers, draining the tank, and then refilling it with DI water. The fill-and-drain cycle is typically repeated 8 to 10 times. An overflow dump rinse (ODR) combines OR and QDR in a single rinse process: wafers are transferred from a chemical bath to a rinse tank filled with DI water and the tank is then sequentially overflowed, drained, and refilled with DI water. The fill-overflow-drain sequence is repeated 8 to 10 times.

Figure 2: Four possible rinse scenarios for the RCA standard clean. All except the immersion spray rinse are commonly used in semiconductor manufacturing.

In all three processes, wafers are transferred from cleaning or etching chemical baths into a rinse tank that has already been filled with DI water. The QDR and ODR processes also often make use of overhead sprays to help rinse residues from wafer surfaces, cassettes, and rinse-tank sidewalls during the drain step. In contrast, the immersion spray rinse (ISR) process involves transferring wafers into an empty rinse tank with the drain open and using overhead showers to spray the wafers with DI water at a rate of 25­30 L/min.⁶ After spraying has continued for 0.5­1 minute, the tank is filled with DI water.

Optimizing Rinse Methods

By definition, any optimized rinse strategy must rinse wafers as well as or better than the best methods currently in use. The basis for evaluating potential process changes is data acquired in the fab under production conditions. Such data can include the results of a wet-tool water-use survey; detailed measurements that identify the quantity and type of contaminants in rinsewater as a function of rinse time and DI-water use; and wafer surface measurements of defects, metal and organic contaminants, and oxide etch uniformity. Tests measuring device electrical characteristics to determine what effect, if any, optimized rinse processes have on device yield are optional.

Wet-tool water-use surveys, which often lead to large savings in DI-water use, involve measuring flow rates as a function of tool utilization. Even when tools are not processing wafers, some DI-water flow must be maintained to prevent bacteria formation in the rinse tanks. Studies performed by semiconductor manufacturers and tool suppliers indicate that idle flow rates of 0.5 to 1 L/min are sufficient for this purpose, although fabs typically use approximately 5 L/min. Reducing these flow rates by only 1 L/min in a 200-mm fab would save more than 6 million liters of DI water per year. This type of optimization does not require requalification of the process flow, making it easy to implement.

Specific methods for evaluating rinsewater include conductivity (or resistivity) and pH measurements, liquid particle counts, and inductively coupled plasma mass spectroscopy (ICP-MS) to determine quantities and types of contaminants. Rinse process optimization requires such data to determine what effects a new rinse strategy will have on wafer surface quality. Information on contaminant concentrations in waste streams is also useful in determining how rinsewater is segregated and treated for recycle and reclaim.

Wafer surface analysis correlates changes in rinsewater contamination levels with wafer surface quality and cleanliness. Relevant measurements include total x-ray reflection fluorescence (TXRF) for surface metal concentrations, light-point defect (LPD) tests to detect particles, ellipsometry for oxide etch uniformity, mass spectroscopy for organic contamination, and time-of-flight secondary ion mass spectroscopy (TOF-SIMS) to determine wafer surface levels of light elemental residues such as fluorine. LPD measurements are commonly used to determine how effective a process is at removing particles following SPM, SC-1, and HF etch cleaning steps, while TXRF is used to determine effectiveness at eliminating surface metal on wafers following SPM, SC-2, and HF etch. Light-scattering metrologies determine oxide thickness and the effect rinse process parameters have on SiO^₂ etch rate uniformity. Mass spectroscopy is useful for determining light (low-electron-density) materials such as organics and fluorine, which are difficult to observe using x-rays. In this way, residues from HF, solvents, and photoresist that may be left on the surface after rinsing are detected.

Rinse Optimization Studies

Studies of three post-SPM rinse processes—one standard and two optimized—were performed to illustrate the effectiveness of the rinse optimization techniques described above. The SPM step was chosen for study because the SPM chemistry is difficult to rinse from wafer surfaces, and qualification of post-SPM rinses requires data on LPDs and surface metal contamination levels. In addition, in most fabs, the rinse recipe used following SPM is also used after SC-1 and SC-2. The results presented here for post-SPM have also been demonstrated for post­SC-1 and post­SC-2 rinses.

Test Procedures. The processes being evaluated were run on a fully automated, 200-mm wet bench that consisted of an SPM module, a rinse tank, an integrated spin-rinse dryer, and an input-output wafer-transfer area. Fifty 200-mm wafers were used for most of the tests. Depending on the rinse sequence being investigated, the wafers were used as received or coated with resist, exposed to a typical implant, and ashed. The wafers that were not coated were tested for particles before and after rinsing; the coated wafers were tested only after rinsing. All TXRF measurements were performed only after processing and rinsing.

The standard rinse recipe used as a control incorporated a 1-minute preflow followed by six ODR cycles. The drain time between each OR cycle was 3 seconds, the DI-water flow rate in the rinse tank was 54 L/min, the flow rate of the overhead showers was 27 L/min, and the temperature of the DI water was ramped from 50° to 22°C. The standard rinse process was completed in 8 minutes and consumed 444 L of DI water while processing 50 200-mm wafers.

Optimized rinse strategy number one was a QDR with no preflow and no overflow cascade. The number of dumps used was conductivity driven and usually was about four for current bench designs. For this study, the drain time between cycles was increased from the 3 seconds used in the standard rinse to 10 seconds. The QDR process was completed in 2.6 minutes and consumed 108 L of DI water while processing 50 200-mm wafers. Measurement results indicated that this optimized rinse strategy can potentially save significant amounts of water and reduce rinse cycle times. However, the possibility of performance enhancements using this type of rinse method is limited by the amount of water carryover from dump to dump, the tank's volume and component geometry, and the rinse programming capability of the wet bench.

Optimized rinse number two, known as the water-saving shower technique, or WASH, required modification of the wet bench to perform the rinse steps. The unique requirements of the process necessitated increasing the flow to the spray bars by combining hot and cold water sources. The resulting mix of tepid water was around 45°C, which is not hot enough to seriously affect diffusion-controlled rinse processes, should there be any. The WASH technique also required programming the bench spray, fill, and dump steps in combinations not normally available.

At the start of the process, the wafers were lowered into an empty rinse tank, which can be empty from the last rinse operation; there is no need to prefill the tank with clean water only to empty it again. When the wafers were in place, high-velocity, high-coverage sprays were turned on with the drain open. After 30 seconds, the sprays were turned off, the drain was closed, and the tank was filled with DI water from inlets at its base. When the tank was full, it was drained again and the overhead sprays were turned on for an additional 20 seconds to complete the rinse process.

The principle behind the WASH technique is that showering is much more efficient than bathing. Using it for post-SPM is probably the best way to demonstrate its capabilities. In this rinse step, wafers above 100°C and coated with sulfuric acid are showered with droplets of water. Heat from the surface liquid and the chemical reaction creates small explosions of steam, and a dilution of the chemistry occurs with the expulsion of droplets of the SPM/water mix. Particles, if not ballistic, become dislodged and stream down the wafer. The wafer is rinsed with hot water until it cools. Continued spraying impacts the surface in a highly turbulent interaction. The WASH process studied also includes a tank-filling step to allow for any immersion processing (e.g., the use of megasonic energy), although results so far have shown this step to be unnecessary.

Study Results. Table I compares rinse cycle times and DI-water consumption for the standard ODR process, optimized strategy number one (QDR), and optimized strategy number two (WASH). The standard post-SPM rinse process consumed 411 L of DI water and was completed in 8 minutes, compared with 108 L and 2.6 minutes for the optimized QDR and 54 L and 1.3 minutes for the WASH. Figure 3 plots DI-water use as a function of rinse cycle step for each of these rinse strategies. In this figure, the water consumption and rinse time requirements for the two optimized rinses are worst-case values, since SPM rinsing is particularly difficult, not because of the chemistry's viscosity or diffusion-layer mixing delays, but because SPM is very concentrated. Chemistries with high concentrations of fluorides show rinse conductivity curves with nearly identical functional forms, although at about 20% of the value of SPM curves because of the differences in concentration and conductivity of the two solutions.

Figure 3: DI-water consumption as a function of rinse cycle step for three post-SPM rinse processes: a standard ODR, an optimized QDR, and the WASH technique.

Figure 4: Conductivity as a function of rinse cycle step for three post-SPM rinse processes: a standard ODR, an optimized QDR, and the WASH technique. Conductivity is plotted on logarithmic scale.

In Figure 4, rinsewater conductivity is plotted as a function of rinse cycle step for the three rinse processes. The figure clearly demonstrates that conductivity decreased more rapidly during the QDR process than during the ODR process, which indicates that cascade overflows do not effectively remove SPM residue from wafer surfaces. In addition, the 10-second drain time used in the QDR allowed more SPM residue to drain out of the rinse tank than the 3-second drain in the ODR. When the standard rinse process was used, SPM residue remained trapped at the bottom of the rinse tank after draining, and when the tank was refilled during rinse cycle steps two through five, SPM residue recontaminated the wafers.

By increasing the drain time to 10 seconds and using overhead spray showers during the drain, the optimized QDR process forced SPM residue out of the rinse tank so that in subsequent process steps the wafers were exposed to cleaner water, resulting in increased rinse effectiveness. Figure 4 also reveals that the WASH technique is even more effective than the optimized QDR for removing SPM residue. The WASH process reached the baseline conductivity in 1 minute 20 seconds and used 54 L of DI water, compared with 5 minutes and 243 L for the standard ODR and 2 minutes and 80 L for the QDR process.

Conductivity data are used to determine recycling/reclaim and waste stream segregation strategies. In any rinse process, water clean enough to be recycled could contribute to a fab's water conservation efforts. Although both of the optimized strategies and the standard rinse process can produce some wastewater suitable for reuse, the WASH process is particularly compatible with recycling because it is extremely efficient at removing contaminants in the early rinse steps and at separating this wastewater from that of later, cleaner rinse steps. The first step in the process removes 99.9% of an SPM solution in about 13.5 L of water. Further data show that 99.8% is removed in 10 L of water in 20 seconds. These numbers are very dependent on the tool's component design and can be improved with little engineering. In one fab, the total water used per wafer during a WASH process, once water regained via recycling has been taken into account, has approached 0.3 L. When rinsing weaker chemistries than SPM, spray times can be reduced to <10 seconds for both steps, water use to <0.1 L per wafer (with recycling), and total rinse process time to <1 minute.

The results of subsequent wafer surface analyses validated the conductivity test findings that optimized rinse strategies performed as well as or better than the standard process. The TXRF data for the WASH, optimized QDR, and standard ODR processes in Figure 5 show that the distribution of metals on the wafers was statistically uniform among bare wafers and coated, ashed, and stripped wafers rinsed by the three procedures. As shown in Table II, LPD measurements performed on split lots also yielded results that indicated the rinse processes' effectiveness, which was not surprising since oxide-coated wafers are known to exhibit good LPD performance independent of rinse strategy. LPD formation is generally dependent on the cleanliness of the wet-tool minienvironment, wafer handling, and dryers.

Figure 5: TXRF surface metal contamination results for blank and photoresist-coated and ashed wafers that were cleaned in SPM and rinsed using the ODR, QDR, or WASH process.

Conclusion

Immersion wet benches equipped with rinse tanks are notoriously wasteful of DI water. In an attempt to discover viable ways to conserve water, two alternatives to the traditional rinsing recipes were evaluated. The first is an optimized QDR process that eliminates flows. Detailed rinsewater analysis showed that quick dump rinsing (coupled with the use of overhead spray showers) is faster and more efficient than overflow rinsing for removing SPM chemical residue from wafer surfaces.

An important consideration in evaluating rinse processes is the drain time between cycles. Too short a drain time allows chemical residue to remain in the rinse tank. This residue is then mixed with in-flowing DI water and revisits the wafer surface. When overhead spray showers were used during draining in the optimized QDR process, superior rinse performance was obtained using less water in less time. In this study the rinse cycle time for post-SPM rinsing was cut almost in half and water use dropped to 50% of the standard value. Moreover, implementing the QDR process does not require that existing wet benches undergo software or hardware modifications, allowing fabs to achieve immediate reductions in water use and processing times.

The second alternative, the water-saving shower, or WASH process, can provide even greater savings in DI-water use, exceeding the goals established by the SIA's International Technology Roadmap for Semiconductors beyond 2012, the last mapped year. In this study, the WASH process reduced water consumption to 15% of the standard value. Recycling of the waste streams from all but the first spray step resulted in a 92% reduction in water use. Tests have shown that there are no technological barriers to implementing the WASH process. With proper tool design, the spray time can be reduced by at least another 50%, bringing the reduction over the standard process to 96%. Fabs can therefore achieve a correspondingly significant increase in manufacturing capacity.

References

1. S Bhat, B van Eck, and V Menon, "Cost Models for Gas and Vapor-Phase Wafer Cleaning," in Proceedings of Microcontamination 92 (Santa Monica, CA: Canon Communications, 1992), 588­597.
2. R Chiarello et al., "Optimization of Post­Sulfuric Acid/Hydrogen Peroxide Mix Rinsing," in Proceedings of the MRS Symposium 477 (Warrendale, PA: Materials Research Society, 1997), 533.
3. R Hall et al., "Improving Rinse Efficiency with Automated Cleaning Tools," Semiconductor International 19, no. 12 (1996): 151­160.
4. J Rosato et al., Proceedings of the Electrochemical Society 94-7 (1994), 140­152.
5. SN Kempka, "Evaluation of Overflow Wet Rinsing Efficiency," in Proceedings of Microcontamination 94 (Santa Monica, CA: Canon Communications, 1994), 225­234.
6. R Parker, R Chiarello, and D Gomez, "Extreme Rinse Optimization," in Proceedings of the Semiconductor Pure Water and Chemicals Conference (Sunnyvale, CA: SPWCC, 1998), 323­341.

Ron Chiarello, PhD, is a physicist at Stanford University (Palo Alto, CA), the industrial liaison for the NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing at the University of Arizona (Tucson), and research program manager for the Interface and Defect Science Laboratory (Stanford University). A consultant to International Sematech since 1996, he has published more than 50 papers on his work in biophysics, surface science, electrochemistry, geochemistry, and semiconductor device processing. Chiarello received a BS in physics from the University of California (Santa Barbara) and an MS and a PhD in physics from Northeastern University (Boston). He is a NATO fellow and has been recognized by the Department of Energy and Argonne National Laboratory (Argonne, IL) for excellence in research. (Chiarello can be reached at 415/242-3230 or ronc@stanford.edu.)

Russ Parker, PhD, is a chemist and systems integration engineer for the biosciences products division of Agilent Technologies in Palo Alto, CA, where he has worked since 1999. He was with Hewlett-Packard for 25 years in medical product development, printed wiring board R&D, and cleanroom support. Parker has published papers on rinse optimization and water recycling in several journals and publishes a Web page with results on his most recent recycling investigations. He received a BS in chemistry from Trinity College in Hartford, CT, and an MS and a PhD in analytical chemistry from Purdue University in West Lafayette, IN. (Parker can be reached at 650/857-3383 or russ_parker@agilent.com.)

Mike Tritapoe is a senior staff member in the environmental department of Advanced Micro Devices (AMD) in Austin, TX. With AMD since 1994, he specializes in the field of environmental engineering in semiconductor manufacturing, focusing on water, wastewater treatment, water conservation, and wet-tool process rinse optimization. He works with Sematech, for which he has conducted studies on surface preparation and water-use optimization and conservation. Tritapoe is a mentor for the NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing at the University of Arizona (Tucson) and is a licensed professional engineer in the state of Texas. He received a BS in mechanical engineering and an MS in environmental engineering from Brigham Young University in Provo, UT. (Tritapoe can be reached at 512/602-4963 or michael.tritapoe@amd.com.

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