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TECHNICAL PROGRAMSThe following list highlights the conferences, symposia, workshops, and similar activities taking place during the week of Semicon West 2000. The San Francisco events appear first, in chronological order, followed by the San Jose listings. The schedule is subject to change, so for the latest information, check SEMI's Web site at http://www. semi.org.
SAN FRANCISCO SUNDAY, JULY 9 8 a.m.5 p.m. Ergonomics Design Guidelines for the Semiconductor Industry: An Introduction to SEMI S8 and SESC (continues July 10 until noon) S.F. Marriott Hotel Instructor: Joe Selan, Advanced Ergonomics
15 p.m. Workshop on Gas Distribution Systems S.F. Hilton and Towers Program Chair: Jack Martinez, NIST MFC Reliability John Savadkouhi, Millipore
The White Box, the Answer for Gas Distribution Systems to Facilitate Factory Control William White, FuGasity Performance and Cost Comparison for Various Bulk Electronic Specialty Gas Delivery Systems Solutions Rick Udischas, Hwa-Chi Wang, M. Xu, M. Munson, and G. Doddi, Air Liquide The Performance of Two Purification Media in Their Removal of Impurities from Inert Gases Armando Colorado, Millipore Progress Report: Thermophysical Properties of Semiconductor Manufacturing Process Gases John Hurly and Michael Moldover, NIST
An Evaluation of Calibration Stabiliy Using an Automated APIMS Brian Warrick and James Borkman, Proair
High-Flow Delivery Systems for Bulk Specialty Gases Belgin Yucelen, Joseph Vininski, and Robert Torres, Matheson Tri-Gas
MONDAY, JULY 10 8 a.m.noon Copper Interconnect Status S.F. Hilton and Towers Program Chair: Mazhar Hussain, Texas Instruments
Copper Integration Issues in Manufacturing Michael Armacost, IBM Microelectronics
The Role of Copper Interconnect in the Semiconductor Roadmap Requirements: A Critical Evaluation Ken Monnig, International Sematech
Copper Contamination Elimination: Wafer Backside, Bevel/Edge, and Exclusion Zone Cleaning Israel Ybarra, International Sematech; and Gaurav Virendra Gupta, SEZ America
Copper CMP Solutions for 0.18 µm and Beyond Savitha Nanjangud, Applied Materials
A Study of Dual-Damascene Reactive Ion Etch Defect Density S. Seymour, IBM Microelectronics; and J. Bowers, Lam Research
Integrated Copper ECD Chemistry and Bath Management System O. Blachier and B. Roberts, BOC Edwards; and A. Athalye and W. Huang, BOC Gases Technology
8 a.m.5 p.m. Silicon Wafer Symposium S.F. Hilton and Towers Program Chairs: SooKap Hahn, Pacrim Technology; Howard Huff, International Sematech; Lubek Jastrzebski, Semiconductor Diagnostics; and John Matlock, Komatsu Silicon Silicon Wafers for the Mesoscopic Era Howard Huff, International Sematech
Silicon Wafer: An Industry at the Crossroads--Technology or Commodity, Which Way to Turn? John Matlock, Komatsu Silicon
Silicon-Pulling Technology for 2000+ Kyon-Min Kim, LG Siltron and KMK Associates
Advanced Developments in Epi Wafers and Their Applications Roxanne Dulas, Wacker Siltronic
Large-Diameter Epi Wafer Solutions for the New Millennium--A Roadmap for the Meeting Parametric and Manufacturing Cost Challenges Gregory M. Wilson, MEMC Electronic Materials
Benefits of Nondestructive Resistivity Testing in Silicon Epitaxial Wafer Quality Joshua Tower, QC Solutions; and Margery Anderson and Amber Crellin-Ngo, Fairchild Semiconductor
A Novel Temperature Measurement on Silicon Wafer by Phase Estimation of Acoustics Wave during RTP Yaoqing Yang, Jookyhua Kang, Jiang Yan, and Guanghan Xu, University of Texas at Austin
300-mm Wafer Carrier Performance Evaluation Tracy Niebeling, Entegris
SiGe for Mainstream Semiconductor Manufacturing David C. Ahlgren, IBM Microelectronics
Process Control of SiGe HBT Structures by X-Ray Diffraction Tom Ryan and Chris Moore, Philips Analytical; and Paul Fewster, Philips Research Laboratories
Silicon-on-Insulator-Materials and Applications George K. Celler, Lucent Technologies
Optical Metrology on SIMOX-SOI Wafers Mike Alles, Ibis Technology
Buried-Layer Substrates: Economically Enhancing Device Performance Leonard Rubin, Eaton
Monitoring of Silicon Wafer Quality with Noncontact, Nonevasive Methods: Surface Photovoltage (SPV) and Contact Potential Difference (CPD) Corona Lubek Jastrzebski, Semiconductor Diagnostics
Measuring Silicon Wafer Nanotopology--How and Why? John F. Valley and Chris L. Koliopoulos, ADE Place Shift
A Combined Optical and Electrical Approach to Gate Dielectric Metrology Clive Hayzelden, KLA-Tencor
You Never Know What You'll Find on a Wafer E.L. Principe, Yuri Uritsky, and C.R. Brundle, Applied Materials; and D.F. Paul, D.G. Watson, and K.D. Childs, Physical Electronics
Symposium on Contamination-Free Manufacturing for Semiconductor Processing S.F. Hilton and Towers Program Chairs: Sowmya Krishnan, Ultra Clean Technology; and Ahmed A. Busnaina, Clarkson University
Contamination Reduction for 300-mm Processes Tadahiro Ohmi, Tohoku University
Defect Reduction Methodology for Advanced Copper Dual-Damascene Oxide Etch P. Biolsi, IBM Vermont; and S. Ellinger and D. Morvay, Lam Research
A Nondestructive Method of Measuring High-Aspect-Ratio Features on High-Density Products Dave Chen, Edward Hanson, Robert Johnson, and Susan Wahdan, Dominion Semiconductor
Gas Delivery System Uptime Improvement by Purification of High-Pressure HCl Gas Mitch Sisemore and Jim Boler, National Semiconductor; and Kent Daniel, Jeff Hardin, Steve Smith, and Kareem Vakhshoori, Millipore
On-site Process Gas Measurements of Moisture and Particles in Corrosive Gas Distribution Lines Allen Zdunek, D. Znamensky, A. Barajas, J. Girard, and M. Bartolomey, Air Liquide; and Janice Edler, IBM
Revolutionary Cylinder Gas Delivery System for UHP Applications Ben Hetzler, John Irven, Ron Pearlstein, J. Stienstra, and D. Zheng, Air Products and Chemicals
Reactivity of Phosphine with Point-of-Use Filters of Different Composition Steve Mankowsky and Gregory H. Leggett, Millipore
Lunch, with poster session (presentations by Pall, Aeronex, Ion Systems, International Sematech, Meeco, Princeton University, Deflex, Kyzen, BOC Edwards, CT Associates, and Beta Squared
Current and Future Challenges for Front-End Semiconductor Wafer Cleaning Glenn W. Gale, IBM assignee to International Sematech
The Mechanics of Brush Scrubbing and Particle Removal in Post-CMP Cleaning Kristan Bahten and Dan McMullen, Rippey
Reduction of Edge Defects in a High-Volume Production Environment Using the Lam OnTrak Wafer Cleaner Gary J. Banks and Peter Carr, MiCRUS Semiconductor; and Jeffrey Farber and Richard Kurjanski, Lam Research
Contact and Noncontact Cleaning Mechanisms in FEOL and BEOL A. A. Busnaina and N. Moumen, Clarkson University
CMP Process Control Using Spectroscopic On-line Monitoring Todd A. Cerni, Particle Measuring Systems
Fluoropolymer (PFA) Contamination in Semiconductor Processing L. Crenshaw, Richard Chatten, and John Imbalzano, DuPont
Evaluation of Melt-Blown Polyprophlene Graded Depth Filters in the Reduction of Large Parfide Counts (LPC) in CMP Slurry Applications Thomas Gutowski, Anthony Shucosky, and Mark Gogol, NSF Filterie Electronics; and Jeff Wilmer and Eric Wilkins, MEGA Systems and Chemicals
Practical Negotiating Skills for Semiconductor Professionals S.F. Argent Hotel Instructors: Robert J. Laser and Stanley N. Sloan, Alliance Management Consultants
Semiconductor Processing Overview S.F. Argent Hotel Instructor: Anne Miller, Semiconductor Services
8:30 a.m.5:30 p.m. Lithography Challenges and Opportunities S.F. Hilton and Towers Program Chair: Harry Levinson, AMD
The International Technology Roadmap for Lithography Harry Levinson, AMD
Resist Materials: A View of the Future Grant Willson, University of Texas at Austin
Advanced Reticle Technology Issues Chris Spence, AMD
Challenges of Membrane-based NGL Masks Pawitter Mangat, Motorola
The Real Lithography Challenge: Cost of Ownership Gil Sheldon, John Canning, Ed Muzio, and Phil Seidel, International Sematech
The Reduction and Control of Process-Induced Overlay Errors John Cossins, ASM Lithography
State-of-the-Art Lithography Control Costas Spanos, UC Berkeley
Focusing System Design to Diminish the High NA/Low DOF Dilemma Yuan Zhang, Canon
Chemical Vapor Depositon for Integrated Circuits S.F. Argent Hotel Instructor: Ted Kamins, Hewlett-Packard Laboratories
Improving Environmental Performance of Wafer Manufacturing Processes (in cooperation with SIA) S.F. Hilton and Towers Program Chairs: Larry Zazzera, 3M; Jerry Meyers, Intel; and Peter Maroulis, Air Products and Chemicals
Session A: Chamber Clean Optimization Study of Reducing PFC Emissions Using C3F8 PECVD Chamber Clean and Applying the Taguchi Method to Get the Optimal Conditions Wei Jen Liu, TSMC
CVD Chamber Cleaning: A Critical Comparison of Processes and Gases Charles C. Allgood and Michael T. Mocella, DuPont Fluoroproducts
Minimizing PFC Emissions from Existing PECVD Tools: Optimization of the Chamber Clean Process of Record Andrew Johnson, William Entley, and Raymond Vrtis, Air Products and Chemicals
Session B: Understanding and Controlling F2 and HAP Tool Emissions Continuous, Real-time Detection of Molecular Fluorine Emitted as a Byproduct of CVD and Etch Processes Curtis Laush, Radian International; and Vic Vartanian, Laura Mendicino, and Paul Brown, Motorola
Evaluation of the BOC Edwards Thermal Conditioning System for HAPs Abatement Mat Waltrip, Applied Materials; and Mike Czerniak and Derek Baker, BOC Edwards
Developments in F2 Abatement Using Point of Use Water Scrubbers Josep Arno, ATMI
Understanding Fluorine Gas Emissions and their Control Rod Gravley, IDC
Evaluation of the Exhaust Gas from an Etcher and Catalytic Decomposition System Shin Tamata, Hitachi America
Lunch
Session C: New Tools and Systems An Environmentally Safe and Economically Cost-Effective IPA Vapor-Dryer for Future Surface Preparation Challenges Evanson Baiya, John Rosato, and Rao Yalamanchili, SCP Global Technologies
A Modular Environmental Design and Decision-Support Tool (EDDT) for Semiconductor Manufacturing Nikhil Krishnan, UC Berkeley
Session D: Abatement Technology Catalytic Solutions for Control of Vapor-Phase Emissions During Semiconductor Manufacture Roy Brown and Joe Rossin, Guild Associates
Water and Energy Usage Reduction in Point-of-Use Abatement Equipment Laura Mendicino, Motorola; and Eric Rieske, ATMI
Characterization and Optimization of a Thermal Oxidizer VOC Abatement System Operating at Low Destruction Efficiency Russell Seguin, AMD
Point-of-Use Catalytic Oxidation for the Reduction of VOC Emissions Christopher Beatty and Bronwyn Moore, Hewlett-Packard
15 p.m. Low-k Dielectric Materials Technology Conference S.F. Hilton and TowersProgram Chairs: Victor Ku and Sompath Purushothaman, IBM Microelectronics
The Challenges in Low-k and Copper Integration in Manufacturing Jim Ryan, IBM Microelectronics
Development of Low-k Material Etch Process for Dual-Damascene Applications Yan Ye, Applied Materials
Relative Merits of CVD vs. Spin-on Low-k Deposition Neil Hendricks, ATMI
Pulsed Plasma and Hot-Filament CVD Dielectrics Karen Gleason, MIT
An Evaluation of Low-k Materials for Interconnect Roadmap Requirements Jeff Wetzel, International Sematech
Characterization of Low-k Dielectrics for Advanced Interconnect Paul Ho, University of Texas at Austin
Copper Dual-Damascene Interconnects with Low-k (<3.0) Dielectrics Using FLARE and an MSQ Hard Mask Toshiaki Hasegawa, Sony Japan
TUESDAY, JULY 11 8 a.m.noon STEP: The CIM Framework--From Standards to Practice S.F. Marriott Hotel Instructor: Bob Hodges, Texas Instruments
Design Practices for Higher Equipment Reliability S.F. Argent Hotel Instructor: Vallabh Dhudshia, Texas Instruments
8 a.m.5 p.m. CMP Technology for ULSI Interconnection S.F. Hilton and Towers Program Chairs: SooKap Hahn, Pacrim Technology; Frank B. Kaufman, Cabot; Kathleen A. Perry, Obsidian; and Manabu Tsujimura, Ebara
Enabling Planarization for the 21st Century: Opportunities, Challenges, and Alternatives Frank B. Kaufman, Cabot
Challenges of CMP Process Integration in Advanced DRAM Manufacturing Champion Yi, ProMOS Technologies
Direct Bonding of Cu and Au for Next Generation of Packaging Tadamoto Suga, University of Tokyo
Selete 300-mm Program Summary and Overview of New Program (130-nm/300-mm Program) Ken-ichi Kawashima, Shigeru Kobayashi, and Riichiro Aoki, Selete
Process Consumables Technology Requirements for Advanced CMP Processes Ara Philipossian, Intel/University of Arizona
Standard CMP Patterned Wafers, Metrology, and Characterization--Who Needs Them Anyway? Taber Smith, SKW Associates; and D. Okumu Ouma, Lucent Technologies
Overview of Methods for Characterization of Pattern Dependencies in Copper CMP T. Park, T. Tugbawa, and D. Boning, MIT
Chemical Mechanical Planarization by a Rotary, Fixed-Abrasive Process Norio Kimura, Yutaka Wada, Masao Hodai, Manabu Tsujimura, and David K. Watts, Ebara
Is Buffing Really Needed for Modern CMP? Michael Ravkin, Lam Research
A Comparison of Velocity Profiles for CMP Mechanisms Tim Cleary and Chris Barns, SpeedFam-IPEC
CMP Performance Using Semirigid Abrasive Wheel Katsunori Ishii, Sony
Advanced CMP Metrology for the Copper Era Lanhua Wei, Sam Lee, and Wenge Yang, Therma-Wave
Integrated Metrology System for Oxide Erosion, Residuals, and Dishing in Copper CMP Balan Srinivasan and Fred Stanke, Sensys Instruments
New Pad Conditioning Disk Design Delivers Excellent Process Performance While Increasing CMP Productivity Chad C. Garretson, Steven T. Mear, Jeff Rudd, Tom Osterheld, and Dan Flynn, Applied Materials; and Brian Goers, Vince Laria, Robert D. Lorentz, Stan A. Swenson, and Timothy W. Thornton, 3M
A Combined Slurry and Pad Approach to Consumables Development Karl Robinson, Cabot
A Highly Selective Oxide to Nitride Slurry for Shallow Trench Isolation and the Influence of Polishing Conditions S.V. Babu, Clarkson University; William G. America, Eastman Kodak; and R. Srinivasan and R. Her, Ferro
Novel Applications of Copper CMP Maria Peterson, EKC Technology
Preparation of Novel Metal CMP Slurries with High Performance Nobuo Kawahashi and Masayuki Hattori, JSR
POU Filtration Using Solaris Technology Geanne Vasilopoulos and Zhenwu Lin, Millipore
8:30 a.m.noon Equipment and Materials Market Briefing Moscone Center
Semiconductor Market Outlook and Trends Fred Zieber, Pathfinder Research
Semconductor Equipment Market Outlook and Trends TBD, SEMI
Semiconductor Materials Market Outlook and Trends Elizabeth Schumann, SEMI
9 a.m. 5 p.m. Fundamentals of Thermal Processes S.F. Argent Hotel Instructor: Charles Johnson, PTI Seminars
Understanding and Using Cost of Ownership S.F. Argent Hotel Instructor: TBD, Wright Williams & Kelly
15 p.m. STEP: Qualifying Equipment Productivity--the SEMI E79 Standard S.F. Marriott Instructor: Jim Irwin, Irwin Consulting
Welcome/Introduction Jim Irwin, Irwin Consulting
Economics of Equipment Productivity from the Equipment Supplier Jim Irwin, Irwin Consulting
A User's View of Equipment: Productivity Improvement as a Strategic Advantage to the Equipment Manufacturer TBD
In Pursuit of Efficiency (Integrating SEMI E10, SEMI E58, and SEMI E79 to Optimize Equipment Performance) T. Pomorski, Fairchild Semiconductor
Tool Availability, MTBF, MTBI, and Parts Availability and How They Impact Productivity Andrew Melnyk, KLA-Tencor
Fab Economics and Productivity Benchmarks Rob Leachman, UC Berkeley
Wrap-Up/Q&A Jim Irwin, Irwin Consulting
Benchmarking as a Management Tool S.F. Argent Hotel Instructor: Kewal K. Verma, BCA International Lithography Solutions for CD Control in the 0.13-µm Era S.F. Hilton and Towers Program Chair: Moshe Preil, KLA-Tencor Lithography Module Solutions
Lithography Challenges in the 0.13-µm Era Moshe E. Preil, KLA-Tencor
CD Control for 0.13-µm Technology John Miller, KLA-Tencor
Reticle Inspection for Low-k1 Lithography Jim Wiley, KLA-Tencor
Manufacturing Benefits and Approaches for Lithography APC William Miller, KLA-Tencor
Semiconductor Supply Chain Management Workshop S.F. Hilton and Towers Instructors: Adeel Najmi, Jose M. Padillo, and Leslie-Ann Asmus, i2 Technologies
Forecasting Techniques for the SEM Industry Moscone Center Instructor: Moshe Handelsman, Advanced Forecasting
36 p.m. EHS Interest Group Meeting S.F. Marriott Meeting Chair: Mike Sherman, FSI International Topic: Exhaust Optimization--The 3-Armed Seesaw: Personnel Protection, Energy Efficiency, and Process Stability
WEDNESDAY, JULY 12
8 a.m.noon MES Workshop 2000: Case Studies in CIM S.F. Hilton and Towers Program Chair: Maryanne Steidinger, Camstar Systems
Improving OEE: A Web-based Approach John Field, Symphony Systems
KLA-Tencor Puts the Web to Work on Quality Control Vladimir Preysman, Datasweep
Improving Fab Performance Joining MES and APS Stew Ballie, JDEdwards
Joining MES and HMI for Efficiencies in Optoelectronics Assembly Laura Villanti, Intellution; and Greg Sowle, Camstar Systems
Best Practices of Semiconductor Industry Leaders Douglas Scott, PRI Automation
Plasma Processing 2000 S.F. Hilton and Towers Program Chair: Daniel Flamm, Microtechnology Analysis Group
Fundamentals and Historical Trends in Plasma Etching and CVD Daniel Flamm, Microtechnology Analysis Group
Energizing the Plasma--Coils and Electrodes, Chucks and Sheaths: the Power Delivery Chain Neil Benjamin, Lam Research
Recent Developments in Etching Processes and Equipment in Japan Makoto Semine, Association of Forecasting Techniques for the SEM Industry
Optical Diagnostic Techniques for Commercial Etching Reactors Vincent M. Donnelly and M.V. Malyshev, Bell Laboratories, Lucent Technologies
New Materials, Integration, Structures, and the Environment Peter Lowenhardt, Applied Materials
MEMS Manufacturing Challenges: Producers Discuss Future Equipment and Materials Needs S.F. Hilton and Towers Program Chair: Steven T. Walsh, Anderson School of Management, University of New Mexico
The State of the Microsystems Roadmap Job Elders, Twente MicroProducts
Lessons Learned by a Microsystems Supplier Bill Higdon, Agilent
The Commercialization of Microsystems 2000 Conference Sid Marshall, Micro Machine Devices
Microsystems Scorecard Roger Grace, Roger Grace Associates
The State of the Art in Bonded Wafer Technology Bo Farmer, NJIT
The State of LIGA Development Jill Hruby, Sandia California
The State of Microsystems from a Suppliers View Joe Brown, Karl Suss
The Microsystems Market from an Emergent Foundry Point of View Steve Scott, MEMS Inc.
STEP: SEMI S2-0200, Safety Guidelines for Semiconductor Manufacturing Equipment S.F. Marriott Program Chairs: W. Richard Gartman, Tokyo Electron America; and Craig Ottesen, Texas Instruments
15 p.m. STEP: SEMI 300-mm Physical and Software Interfaces and Carriers Standards S.F. Marriott Instructor: Margaret Pratt, International Sematech
Introduction Margaret Pratt, International Sematech
Overview of Automation SW Standards Margaret Pratt, International Sematech
Physical Interfaces and Carriers Standards Ron Billings, International Sematech
Compliance Testing--The FIMA Document Lorn Christal, International Sematech
AMHS Standards
Parallel I/O Standards Jack Ghiselli, GW Associates
Carrier Management Standards Karl Gartland, IBM
Wafer-Level Control Standards Blaine Crandell, Texas Instruments
Control Job, Substrate Tracking Enhanced Process Job Jack Ghiselli, GW Associates
Related Activities Margaret Pratt, International Sematech
Q&A with Speakers Panel
SAN JOSE
TUESDAY, JULY 11
9 a.m.5 p.m. Third Annual Semiconductor Packaging Symposium (in cooperation with the Surface Mount Technology Association) (Sessions 58 take place July 12, 8:30 a.m.5 p.m.) S.J. Hilton and Towers
Keynote Address Finally a Little Respect--The Emergence of Packing into a More Critical Role in Semiconductor Manufacturing Dennis McKenna, ChipPac
Session 1: Lead-Free Manufacturing Chair: Raj Pendse, ChipPac
Global Status of Lead-free Market Trends and Legislation in the Electronics Industry David Bergman, IPC
Characteristic of Some Lead-Free Solder Pastes for Microelectronic Package Assembly Paul Hart, Donald Henderson, Karl Puttlitz, Nadia Tonsi, Amit Sarkhel, and Charles Woychik, IBM Microelectronics
Lead-free Wafer Level Chip-Scale Micro SMD Luu Nguyen, N. Kelkar, and Hem Takiar, National Semiconductor
Lead-free Solder for CSP: The Impact of Higher Temperature SMT Assembly Processing Vern Solberg, Tessera
Environmentally Friendly Packaging Solutions Rahamat Bidin, Rosemarie Tagapulot, Carl Nichelle, D. Lao, and Rodel Manalac, ST Assembly Test Services
Session 2: Wafer-Level Packaging Chair: Luu Nguyen, National Semiconductor
The Infrastructure for Wafer-Level Packaging: Current Status and Future Requirements Tom DiStefano, DecisionTrack
Reliability and Thermomechanical Analysis of Compliant Wafer-Level Package Chirag Patel, Georgia Institute of Technology
Backside Contacts for 3-D Wafer-Level Packaging Ed Korczynski, Tru-Si Technologies
Application for WLP at Positive Working Photosensitive Polybenzoxazole Kagehisa Yamamoto, Sumitomo Bakelite
Session 3: New Concepts in Test, Assembly, and Packaging Manufacturing Chair: Vern Solberg, Tessera
Implementation of On-Bonder Curing to Maximize Array Package Manufacturing Productivity Rene Ulrich, ESEC; and Stephen Taylor, Dexter Electronic Materials
The Application of Atmospheric Pressure Plasma to Various Steps in IC Packaging Jason Uner, M. Theriault, C. Carsac, and T. Sindzingre, Air Liquide
Consideration of Fine-Pitch Copper Ball Bonding on Copper Pad Substrates Ralph Binner, ESEC
Development of a Glob Top Encapsulant Suitable for 50-mm Pitch BGA Packages Andrew Hmiel and Sergio Rojstaczer, Advanced Polymer Solutions; and Lee Levine and Pat Marburger, Kulicke & Soffa
Transfer Molding Encapsulation of Flip-Chip Array Packages: Technical Developments in Material Design Tara Miles, Dexter
In-strip Testing and Burr Inspection in the Production of QFP Packages K.K. Khoo, Jayakrishnan Menon, and L.K. Tee, Motorola Malaysia; Reinhilde Alaert, Icos Vision Systems
Session 4: Reliability
Warpage Improvement on the LOC TSOP-II Unbalanced Package ChiKai Chuang, ChipMos Technologies
Encapsulation Reliability of Wire Bonding to Copper Devices Claire Rutiser and Hiroshi Munukata, Kulicke & Soffa; and Nobuyuki Sashida, Sumitomo Bakelite
Design Optimization of Thermally Enhanced Flip-Chip PBGA BiChu Wu, ITRI Taiwan
Analysis of a PBGA Board Interconnect Failure John Turn, Guna Selvaduray, Steve Vukazich, and Peiman Amoukteh, San Jose State University
Real-World Fatigue Life of Ceramic Surface Mount Packages: The Power Cycling Advantage Gregory Martin, Harry Harrington, Janet Jozwiak, Ellyn Ingalls, Lewis Goldmann, Marie Cole, and Jeffrey Coffin, IBM Microelectronics
Design Optimization of BGA Packages Dawit Solomon and Timothy Leung, AIT (formerly Hana Technologies)
Qualification Results of HyperBGA, IBM's High-Performance Flip-hip Organic BGA Kim Blackwell, Thomas Kindl, Hal Lasky, and Ty Youngs, IBM Microelectronics
Session 5: Flip Chip vs. Wire Bond--The Interconnect Dilemma Chair: Guna Selvaduray, San Jose State University
Critical Developments in Flip-Chip Infrastructure and Markets Jan Vardaman, TechSearch International
The Limits of Wire Bond Technology: Is Flip-Chip Attach Now a Prerequisite for Advanced Packaging? Mark Kuzawinski, IBM Microelectronics
40-µm Ultra-Fine-Pitch Bonding in Production: What Does It Mean? Daniel Zanetti, Hans-Ueli Stocker, Lorenzo Parrini, and Peter Hess, ESEC
A New Integrated Manufacturing Technology for Placement of Flip-Chip Devices onto High- Density Substrates Heinz Ritzmann and Gustav Wirz, Alphasem
Performance Aspects of ASIC Packages: Why Flip Chip Will Win the Performance Race Edward Wolf, IBM Microelectronics
Emerging Wire Bond Interconnect Solutions for Copper Matt Osborne and Nikhil Murdeshwar, Kulicke & Soffa
Session 6: High-Density Interconnect Technologies (sponsored by the SMT Association) Chair: Tom Chung, First International Computer
HDI, Interconnect Solutions for the 21st Century Ron Daniels, Miller Freeman
High-Frequency Applications: A Real Challenge for Organic Packages? Stefano Oggioni and Roberto Ravanelli, IBM Microelectronics
Imprint Patterning, an Emerging and Advantageous Technology for Ultra-HDI Substrates George Gregoire, Dimensional Circuits
UltraVia, Thin Film Substrate for Advanced BGA Applications Bill Chou and Solomon Beilin, X-Lam Technologies
Few Chip Modules: Technology Options for System-on-a-Package (SOP) William Shutler, Alberto Parolo, Stefano Oggioni, and Claudio Dall'Ara, IBM Microelectronics
High-Density Substrates for Optimized Module Design Gary Dudeck, Strand Interconnect
Session 7: Wafer Bumping Process Chair: Chung Ho, TFM Module
Critical Developments in Wafer Bumping Infrastructure Fei-Jain Wu, ChipBond Technology
Comparing Eutectic and High Melt Solder Bumps: A Package Assembly Perspective D. Danovich, M. Belazzouz, C. Fortin, P. Langevin, and V. Oberson, IBM Microelectronics Canada
Plasma Etch Process for Flip-Chip Packaging Paul Werbaneth, Genevieve Beique, Tim Engel, and Mark Lis, Tegal
Postreflow Cleaning Process Enhances the Reliability of Flip-Chip Packages Mike Bixenman, Kyzen
2-D/3-D Bump Defect Inspection: Pre- and Postbump Process Verification Jarrad Taunt, Unitive Electronics; and Jeremy Jenum, August Technology
Inspection and Analysis Techniques: Identity Bump Process Issues Joe Savarese, Electroglas Inspection Products
A Technique for Quantitative Analysis of Filler Density in Flip-Chip Underfill Andrew Hmiel, Walt Von Seggern, and Sergio Rojstaczer, Advanced Polymer Solutions
Session 8: Assembly with High-Density Packages (CSP, BGA, DCA) (sponsored by the SMT Association) Chair: Rich Freiberger, ACT Manufacturing
Area Array Packaging Drives Electronic Product Miniaturization Greg Reed, SMT magazine
Components of a Known Good Assembly Jim Rates, Chip Supply
Capabilities of Leading-Edge SLC Flip Chip PBGAs Bernt Hansen, Charles Carey, Donald Burr, Randal Stutzman, Irving Memis, and Yukata Tsukada, IBM Microelectronics
Detailed Discipline Approach to CSP Assembly Process Development Dale Lee, Manufacturers Services
Worldwide Deployment of CSP Assembly Process Paul Wang, Katsuji Takasu, and Shelgon Yee, Solectron
Optimization of the Printing Process for CSP Assembly Ravi Bhat, Murad Kurwa, Alington Lewis, Kazu Nakajima, YongMei Wang, and Sammy Yi, Flextronics
THURSDAY, JULY 13
8:309:30 a.m. Equipment and Materials Market Briefing S.J. Convention Center
8:30 a.m.12:30 p.m. 9th Annual Manufacturing Test Conference S.J. Hilton and Towers Program Chairs: Wayne Tan, AMD; and Bob Durstenfeld, Agilent Technologies.
Keynote Address Structuring the Future of Test for Today's "E-conomy" Jackie Tubis, Schlumberger ATE
Session 1: Test Floor Effectiveness Asset Productivity
The Virtues of Virtual Test for Fabless IC Developers Keith Katcher, NVIDIA; and Gordon Smith, IMS
Strategies for Test on Strip Gordon Mackenzie, Delta Design/Cohu
Modeling of OEE to Improve Back-end Operations Jim Dawdy, Agilent Technologies
Session 2: Test Floor Asset Productivity
Automatic Test Resource Management Sergio Perez, Comdisco Electronics Group
Wafer Probe vs. Final Test: Balancing Leonard Berger and Andy Pierce, Texas Instruments
Dual-Site Testing on a Mixed-Signal Tester David Ganapol, Artest
8:30 a.m.5 p.m. International Packaging Strategy Symposium S.J. Hilton and Towers Program Chairs: Charles Bauer, TechLead; and Randy Braun, Honeywell
Die Products: Poised for Success in Today's Portable Products Larry Gilg, MCC
Materials Requirements for Today's Advanced Packaging and Assembly Charles W. Lin, AdvancPack Solutions
Packaging and Interconnect Needs for Portable Telecommunications Walt Marcinkiewicz, Ericsson
System-Level Drivers for High-Performance Processor and ASIC Packaging Rick Luebs, Hewlett-Packard
Recent Advanced Electronic Packaging Activities in Korea Paik Kyung Wook, Korea Advanced Institute of Science and Technology
Lead Elimination: First- and Second-Level Packaging Implications Thilo Sack, Celestica, Canada
Manufacturing Technology Roadmap for the Networking/Telecommunications Industry Ganesh Sure, Cisco Systems
Consumer Products Electronic Packaging for the 21st Century Masahide Tsukamoto, Matsushita
A Roadmap of Taiwan's Electronic Packaging and Interconnect Industry Shen Li Fu, I Shou University, Taiwan
NEMI Roadmap for Miniaturized Electronic Products Leo Feinstein, NEMI
Build-up Substrate Technology Roadmap Yukata Tsukada, IBM Japan
FRIDAY, JULY 14
8:30 a.m.12:30 p.m. Wafer-Level Packaging Forum: A Hard Look at Chip Scale/Wafer Level Packaging Issues S.J. Convention Center Program Chairs: Tom DiStefano and Vern Solberg, Decision Track Panel: Mike Campbell, BPA; Tom Goodman, Flip Chip Technologies; Linda Jardine, International Interconnection Intelligence; Luu Nguyen, National Semiconductor; Jan Vardaman, TechSearch International; Jim Walker, Dataquest; and Jim Young, Intarsia MicroHome |
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