Measuring and controlling wafer temperature during plasma etching

Many techniques have been proposed to measure wafer temperature in a plasma, but most have drawbacks that limit their usefulness in production environments. The most widely used method is to tape temperature dots or labels that change color at discrete temperatures onto a wafer. The disadvantages of this technique include its unknown contamination risks, limited temperature range, large steps between indicated temperatures, and strong dependence on how the user applies the material to the wafer. In addition, the labels are typically covered with Kapton tape to protect them from the plasma, but trapped air under the tape can lead to the formation of a parasitic plasma and thus give an inaccurate temperature indication.⁴

One relatively new measurement technique, known as the Active Plasma Thermal Optical System, determines actual wafer temperature in real time, but it requires a fiber-optic harness that is tethered to the wafer. Developed by SensArray (Fremont, CA), the system is well suited for R&D applications, where the effort to open the chamber and install the harnessed wafer is rewarded by a wealth of temperature information.⁵ However, to provide useful data for addressing day-to-day temperature-related concerns in a production fab, a measurement technique should require no hardware modifications, tethers, or chamber cleaning after use. Until now, no technique has met those requirements.

This article introduces such a technique, which also was developed by SensArray. In this method, known as arrays of peak temperature indicators (APTI), single-use instrumented wafers are used for profiling peak temperatures across the wafer in situ. During research into the technique's capabilities, process variation tests were run in several metal and dielectric plasma etch tools at Advanced Micro Devices (Sunnyvale, CA). The study, which is described here, showed that peak wafer temperature in a plasma can be measured easily and reliably without taking the system off-line or opening the chamber. The tests also demonstrated the importance of knowing and controlling wafer temperature during plasma etching. Results indicated that wafer temperature rises with increases in the lower-electrode temperature and applied power, and decreases as backside helium pressure is raised.

The plasma etch tools on which the peak temperature indicators were investigated included a high-density plasma (HDP) metal etcher and several dielectric etchers encompassing low- and medium-density plasma (LDP and MDP) sources as well as HDP sources. Several process parameters were varied to demonstrate how peak wafer temperature can be affected by the etch recipe. During the test runs, the instrumented wafers were exposed to normal etch processes having a fixed time of 60–90 seconds.

Metal Etching. Many process variables determine the peak temperature a wafer will achieve during an etching process. An obvious factor is the temperature set point for the chiller connected to the etch tool's lower electrode, where the wafer rests. If heat transfer between the wafer and the electrode is good, this set point determines the initial wafer temperature. Subsequent exposure to heat from ion bombardment and exothermic chemical reactions causes the wafer temperature to rise above this level. Wafer temperature affects sidewall polymer formation and metal linewidth. At low wafer temperatures, polymer precursors tend to condense, causing lines to widen as they are etched, while higher temperatures reduce polymer deposition and cause linewidths to shrink.

The measurement data in Figure 3 show how wafer temperature and linewidth loss depend on the lower-electrode chiller's temperature set point in an HDP metal etcher running a Cl₂/BCl₃/CHF₃ chemistry. The error bars in this and other figures indicate minimum and maximum temperatures across the wafer. In this case, the peak wafer temperature response, measured using peak temperature indicators, was linear to the chiller set point, with a slope close to 1. Linewidth loss does not appear to be linear with set point, but the lower-electrode temperature clearly has a strong effect on the metal linewidths.

If there is a vacuum between the wafer and the lower electrode, heat transfer is very poor. To overcome this problem, the wafer is mechanically or electrostatically clamped to the electrode and a gas such as helium, which has a high coefficient of thermal conductivity, is introduced to raise the pressure behind the wafer. Increasing backside pressure brings the wafer temperature closer to that of the lower electrode, but the benefit approaches saturation above 10 Torr for typical electrostatic chucks.⁶ Figure 4 presents study results indicating how wafer temperature is dependent on backside helium pressure in the HDP metal etcher, which uses an electrostatic clamp. At 12 Torr, the average wafer temperature was 54.4°C, less than 12°C above the lower-electrode chiller's temperature set point of 43°C.

In addition to the lower-electrode temperature set point and backside helium pressure, the radio-frequency power used in a metal etch process also has an effect on wafer temperature. In plasma etch tools, the power output from the generator can be closely controlled. However, only a fraction of that power is actually coupled into the plasma because of losses that occur in cables, the matching network, and other components in the RF path. Because the performance of these components can vary with time or between nominally identical tools, wafer temperature can vary as well.

In the HDP metal etcher used in the study, separate supplies control power delivery to the plasma source (an inductive coil) and the wafer bias. The result of varying source power, presented in Figure 5, and bias power, presented in Figure 6, was studied using wafers equipped with peak temperature indicators. With a backside helium pressure of 12 Torr, power had a small effect on wafer temperature, which rose only 0.9°C for each 100-W increase in source power and 1.5°C for the same increase in bias power. Apparently, adding bias power to increase ion energy increases wafer temperature slightly more than does adding source power to increase plasma density.

Dielectric etchers cause wafer temperatures to increase two to six times more per 100 W of RF power than metal etchers do, probably because metal etchers' power levels are very low compared with the ability of the tools' electrostatic clamp to remove the heat produced by that power. The test runs in which helium pressure was reduced to 3 Torr—crippling the heat-removing capability of the clamp—more clearly revealed the potential heating effect of both source and bias power on wafers undergoing metal etch, with bias power exhibiting a stronger and less linear relationship to wafer temperature than source power.

Dielectric Etching. Compared with metal etch processes, much higher power levels are typically used during etching of dielectric materials such as silicon dioxide, which has a strong silicon-oxygen bond to break. The wafers with the indicators were used to study peak wafer temperatures during dielectric etching in a wide range of tools, including LDP, MDP, and HDP systems. One focus area was the effect that variations in high RF-power levels can have on wafer temperature, which in turn determines such key parameters as selectivity to the mask and to underlayers, via and trench profiles, reactive-ion-etch lag, and susceptibility to etch stop.

In one series of test runs, RF power in an LDP etcher with a mechanical bottom-actuated clamp was varied from 1400 to 2200 W during a high-pressure CHF₃/He/N₂ dielectric etching process. The wafers with the temperature indicators used for these runs had sensors only at the center and were reused at progressively higher RF power levels, each of which caused more indicators to turn black. Figure 7 shows the peak temperatures measured on five different wafers as a function of power level. A reproducible and strongly linear response can be seen, with peak temperatures increasing ~6.0°C for every 100-W increase in power.

The effect of RF power was studied in several other dielectric etch tools, including another LDP etcher that was similar to the one used in the test runs described above, with the notable exception that it had an electrostatic rather than a mechanical clamp. Wafers equipped with the peak temperature indicators calibrated to gauge lower-than-usual temperatures were used in this case to detect the effect of lower power levels. In a test using a damascene etch process, an etch system with a magnetically enhanced reactive-ion-etch technology to achieve an MDP was also investigated. Finally, the bias power in an HDP dielectric etch system was varied while etching several indicator-equipped wafers.

Wafer-average data for all of these systems are shown in Figure 8, and Table I summarizes that data, showing how equivalent power changes caused different wafer temperature responses. Despite great differences in plasma source technology, process chemistry, and lower-electrode temperature set points, the wafers processed in all of these tools reached temperatures of 70° ±30°C across a wide range of RF powers. Perhaps this wafer-temperature uniformity is not surprising—temperatures lower than 40°C are difficult to achieve during dielectric etching because of the heating caused by the high RF-power levels needed to break the strong bonds in inorganic dielectrics. However, temperatures much above 100°C will cause damage to the soft organic photoresist mask. Another similarity evident from Figure 8 is the slope of the least-squares best-fit lines, which were nearly parallel except for that of the data for the LDP etcher with a mechanical clamp. Wafer temperatures in that tool rose more quickly as RF power increased.

Conclusion

In a capability study, indicator-equipped wafers were used to measure peak wafer temperature during plasma processing in a metal etch tool and several dielectric etchers. In other tests, the etchers' lower-electrode temperature set point, backside helium pressure, and RF power levels were varied, and linear correlations were often found between these parameters and wafer temperature. Such data enable process engineers to monitor and compare processes and tools and to achieve the control of wafer temperature that is essential to maintaining critical linewidths and other important etch characteristics.

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