where Y_R is a function of the critical area of a device (A), the random electrical fault density (D₀), and the cluster factor (a). As in 1999, defect budget targets in the 2001 ITRS were calculated on the basis of Y_R. Assumptions in the 2001 revision about systematic-limited yield targets at specific points in the yield-ramp cycle were based on discussions with domestic and international MPU and DRAM manufacturers and carried over from 1999. These assumptions are summarized in Table II.

Budget Category 1999 and 2001 ITRS Cost/Performance MPU Cost/Performance DRAM Production phase Yield-ramp phase end Volume production phase end Y0 (%) 75 85 YR (%) 83 89.5 YS (%) 90 95 Cluster factor 5 5 Chip size 140 mm2 Increasing internode; decreasing intranode

Table II: Defect budget technology requirement assumptions: 1999 and 2001.

In 1999 defect budget targets were quoted on a PID basis. The change to quoting defect budget targets in terms of PWP was made because it is difficult to determine the transfer coefficients that drive PID values from PWP numbers and because most data gathered in 1999 and 2000 were PWP-based.

In order to extrapolate PWP budgets to future technology nodes, shrinking feature sizes and projected increases in both chip size and process complexity (as reflected in the number of mask levels) were taken into consideration in the following PWP extrapolation equation:

This equation was used to project technology node budget values based on a generic 130-nm International Sematech–defined process. In the equation, PWP is in defects per square meter, F is the average faults per mask level, S is the minimum defect size, and n is the technology node. All PWP budget values were defined for the critical defect size of 75 nm. This tends to be a worst-case model, since it assumes that all process steps are performed on devices with minimum geometries, although many process steps are in fact performed on features with more-relaxed geometries. However, because the same tools are used to process devices with both very small and more-relaxed geometries, this worst-case model yields relevant results.

For DRAMs, the random fault density used to calculate faults-per-mask levels (for use in the PWP extrapolation equation) was based only on the periphery (logic/decoder) area of the chip, which is projected in the ORTC to be 45% of chip area at the stated product maturity level through 2002. Because there is no redundancy in the periphery, that portion of the chip must consistently achieve the projected 89.5% random-defect-limited yield. It was assumed that the core (array) area of a DRAM can implement sufficient redundancy so that the overall yield target of 85% can be attained. The MPU and DRAM defect budget targets calculated for a generic metal etch process are shown in Figure 1.

Figure 1: The 2001 roadmap's DRAM and MPU particles-per-wafer-pass defect targets for metal etch by year.

Defect Budget Calculator. A key enhancement to the YMDB section in 2001 is the inclusion of a downloadable defect budget calculator, which is available at the ITRS Web site.¹ This software, developed by Wright Williams & Kelly, allows users to input the minimum critical defect size, random-defect-limited yield target, chip size, number of mask levels, and, for DRAM only, peripheral logic chip area percentage to estimate PWP defect target values by generic process step for a specific product. The calculator uses the same extrapolation method and database used in the roadmap tables. A static example of the calculator is shown in Table III.

Input Parameters User Input Minimum critical defect size (nm) 75 Random-defect-limited yield (%) 83.0 Chip size (mm2) 140 Number of mask levels 25 Peripheral (logic) chip area (%) 100.0 Random D0 (faults/m2) 1356 Random faults per mask 54

Process Step User PWP Target Values (defects/m2) MPU DRAM CMP clean 448 828 CMP insulator 1084 641 CMP metal 1225 983 Coat/develop/bake 196 256 CVD insulator 963 711 CVD oxide mask 1267 872 Dielectric track 308 359 Furnace CVD 549 491 Furnace fast ramp 497 463 Furnace oxide/anneal 321 370 Implant high current 430 430 Implant low/medium current 392 410 Inspect PLY 400 561 Inspect visual 429 579 Litho cell 332 481 Litho stepper 315 319 Measure CD 374 479 Measure film 321 451 Measure overlay 298 439 Metal CVD 585 452 Metal electroplate 302 343 Metal etch 1300 832 Metal PVD 667 496 Plasma etch 1183 881 Plasma strip 547 676 RTP CVD 357 442 RTP oxide/anneal 234 323 Test 91 63 Vapor-phase clean 822 935 Wafer handling 37 27 Wet bench 535 669

Table III: Static example of 2001 yield model and defect budget calculator.

Future Focus. With each technology node, an ongoing validation of random-defect-limited yield PWP and PID budget targets will be required. In addition, methods to model parametric-limited, systematic-limited, and circuit-limited yield mechanisms must be more vigorously investigated in order to address those yield loss issues that are usually dominant during the early phases of a yield ramp.

Defect Detection and Characterization

Inspection tools that meet both throughput and sensitivity requirements are necessary to detect in-line yield-limiting defects during the various phases of production, such as process R&D, yield ramp, and volume production. It is critical that tools have the flexibility to run products at different stages of product maturity in order to achieve maximum return on the extensive capital investment required. Future technology requirements for the detection, classification, and review of process-related defects are addressed in the defect detection and characterization (DDC) section of the Yield Enhancement chapter of the roadmap. Generally, those areas identified as challenges in the previous ITRS revision remain as such.

Patterned-Wafer Inspection. In order to comply with IRC guidelines, the DDC Sub-Technology Working Group relaxed the technology requirements for patterned-wafer inspection throughput and sensitivity in the 2001 ITRS, as shown in Table IV. Even so, existing technologies do not currently achieve these throughput targets at the required sensitivity levels.

Technology Requirements 1999 ITRS 2001 ITRS Throughput (cm2/hr) Sensitivity Throughput (cm2/hr) Sensitivity Process R&D 300 0.3x design rule 300 0.6x design rule Yield ramp 3000 0.4x design rule 1200 0.8x design rule Volume production 10,000 0.5x design rule 3000 1.0x design rule

Table IV: Comparison of patterned-wafer inspection requirements: 1999 versus 2001.

High-Aspect-Ratio (HAR) Inspection. The 2001 ITRS continues to emphasize the critical need for HAR inspection tools to look into the bottom of vias, trenches, and canals for residues, contamination, and other defects. In order to comply with IRC guidelines, technology requirements for HAR inspection sensitivity were relaxed from 0.3x design rule in 1999 to 1.0x in 2001. In addition, line items specifying sensitivity and throughput requirements for process verification and volume production phases were added. In reality, device manufacturers need the best HAR inspection tools to determine the sizes, shapes, and types of material remaining at the bottom of contacts on the order of 0.3x design rule at the rate of one 200-mm wafer per hour during process R&D phases and four 200-mm wafers per hour during volume production phases. Contact aspect-ratio projections for stacked capacitor structures have been provided by the Interconnect ITWG. These projections (presented in Figure 2) show aspect ratios approaching 15 in the near term (before 2007) and 23 in the long term (approaching 2016). Furthermore, added complexity for both via and contact structures increases the inspection challenge, as shown in Figure 3.

Figure 2: Projected stacked capacitor contact aspect ratios versus technology node.

Figure 3: Via structure evolution: comparison between current inspection methods, which should target as-etched 10:1 aspect ratios (a), and future inspection methods, which must target more-complex as-etched >15:1 aspect ratios (b).

Cost of Ownership (COO). A key enhancement to the DDC section of the roadmap is the addition of a metric that targets COO for volume production. COO is measured by cost per wafer scanned, assuming 4 wafers scanned per hour for HAR inspection and 10 wafers scanned per hour for non-HAR inspection. Currently, HAR inspection can only be achieved at the extremely low throughput rate of one wafer per hour and the high COO of $20–$50 per wafer. Therefore, it is not a manufacturable process and is marked red in the roadmap (i.e., no known solution is currently available). Tool cost, fab space occupied, and throughput are major contributors to COO. High COO forces many semiconductor manufacturers to deploy inspection tools in sparse sampling modes, increasing the potential risk of yield loss by failing to identify yield excursions early on and slowing yield-learning rates. Statistically optimized sampling algorithms are needed to maximize yield learning based on inspection tool data.

Wafer Backside Inspection. Based on strong input from the Yield Enhancement ITWG, wafer backside defect inspection criteria have been reinstated in the technology requirements of the DDC section of the 2001 ITRS, after having been removed from the 2000 table update. These criteria are based on lithography depth-of-focus requirements published by the Lithography ITWG. The requirements stipulate the number of particles allowed at critical defect sizes (200 nm through 2004 and 100 nm from 2005 to 2010). The DDC working group believes that particle detection for this metric is not possible for 200-mm wafers because of current backside roughness specifications, but will be possible with 300-mm wafers. Backside particle detection tools that meet ITRS specifications are currently available.

Automatic Defect Classification (ADC). The technical requirements for ADC in the ITRS remain the same as in the 1999 revision, updated to take into consideration the new 130-nm technology node in 2001. Whether ADC is performed on a defect detection or review tool, it can differentiate between various defect types or classes with much greater accuracy than can human operators. However, ADC systems can analyze only a limited number of classifications effectively, and the generation of classifiers is time-consuming. The 2001 roadmap thus continues to recognize the need for improved classification systems. As the industry moves to smaller and smaller defect size requirements, it becomes increasingly difficult to distinguish between defects. Tools are needed that can simultaneously detect and differentiate between multiple killer-defect types at high capture rates and throughputs. Advanced ADC systems should also be able to analyze defect categories for some level of compositional information. Furthermore, the tools should be able to project a potential point of origin for each defect type based on the location of the lot and a given process flow sequence.

Potential Solutions. Although new tools have been introduced since the 1999 ITRS, they have not addressed the requirements for HAR inspection, classification, and characterization of <90-nm defects, which will play an increasingly important role in future technology nodes. The development of novel techniques to detect thin residues at the bottom of HAR structures must be pursued rapidly. Techniques that may offer solutions include holographic imaging, e-beam (scattering or imaging), acoustic imaging, and x-ray imaging. In any case, tools with both sensitivity and throughput capabilities that also can achieve COO targets are needed to function as in-line process monitors.

Yield Learning

The Yield Learning section of the 2001 roadmap (formerly called Defect Sources and Mechanisms) provides an overview of the technology requirements for integrated data management and yield-learning rates at future technology nodes. This section contains several enhancements over the 1999 roadmap.

Integrated Data Management. In the face of increased design and process complexity, developing an optimum strategy for integrated data management (IDM) has been identified as critical for accelerating yield learning from the introduction phase through process and product maturity. IDM must take into consideration circuit design, visible and nonvisual defects, parametric data, and electrical test information to recognize process trends and facilitate rapid root-cause identification of yield loss mechanisms.

Visible and Nonvisual Defects and Parametric Yield Loss. Ever-improving tools are required to detect, review, classify, analyze, and source continuously shrinking visible defects. The affordable detection of nonvisual defects that cause electrical failure but do not leave physical remnants is an increasing challenge. Yield loss attributable to parametric variation within and across wafers has historically been placed in the same category as yield loss caused by nonvisual defects. Techniques must be developed that rapidly isolate and partition visible defects, nonvisual defects, and parametric issues.

Defect-Sourcing Complexity Factor. The defect/fault-sourcing complexity factor introduced in 1999 has been updated in the latest ITRS revision in order to continue to highlight the defect-sourcing challenge. The defect/fault-sourcing complexity factor is defined as the product of the logic transistor density (number per square centimeter) and the number of steps in the integrated process flow (see Table V). As illustrated in Figure 4, the needle-in-the-haystack analogy continues to highlight the challenge posed by the defect/fault-sourcing complexity factor versus critical defect size.

Budget Category Year of First Product Shipment (Technology Generation) 2001 (130 nm) 2004 (90 nm) 2007 (65 nm) 2010 (45 nm) 2013 (32 nm) 2016 (22 nm) Critical defect size (nm) 65 45 33 23 16 11 Logic transistor density/cm2 (106) 14 35 85 210 519 1279 Defect/fault-sourcing complexity factor (109) 7 18 49 128 337 883 Defect/fault-sourcing complexity trend 1 3 7 18 48 126

Table V: Defect/fault-sourcing challenge over key technology nodes.

Figure 4: The fundamental yield challenge: How to source the origin of shrinking defects as chips become more complex.

Data Volume. In light of the explosive growth of yield-related data and their importance for yield management, projected data volumes for future technology nodes have again been included in the ITRS technology requirements table. Key findings from a 1999 International Sematech– sponsored data management system (DMS) assessment study have been included among the roadmap's supplemental materials. Figure 5 summarizes the top R&D issues identified in the survey, listed in the order that they should be addressed. (Although the issues at the bottom of the figure will have the greatest affect on DMS technologies, the infrastructure needed to tackle them depends on addressing the top issues first.) The key areas for R&D investment include:

Figure 5: Summary of R&D issues derived from the 1999 International Sematech DMS survey.

Yield-Learning Assumptions. First included in the 1999 roadmap, yield-learning assumptions were expanded in 2001 to stipulate required yield improvement rates per learning cycle, the amount of time needed to identify and fix new defect/fault sources during yield ramp, and required yield improvement rates per learning cycle for one new defect/fault source per month. The assumptions used in determining these values include keeping yield ramps at current benchmark levels and sourcing new yield detractors within 50% of theoretical cycle time, despite growing chip complexity, higher data volume, new materials, and novel device structures.

New Areas of Research. The Yield Learning Potential Solutions table in the 2001 ITRS addresses the need for new research in automation methods to achieve design, process, and test data correlation; fault-to-defect mapping; design-to-process interaction modeling; process capability analysis; and predictive parametric disturbance modeling.

Wafer Environment Contamination Control

The roadmap's Wafer Environment Contamination Control (WECC) section presents technology requirements for the cleanliness of process materials and the wafer environment based on the findings and analyses of other ITRS sections. In general, this section changed little between 1999 and 2001.

Wafer Environment Control. As projected in the 1999 roadmap, wafer isolation using integrated tool minienvironments and closed carriers is being implemented throughout the industry for increasingly tight design geometries. In addition, optimizing wafer handling through the use of front-opening unified pods (FOUPs) is facilitating factory automation. WECC technology requirements specify wafer target levels for ambient bases, condensables, dopants, and metals for specific process steps.

Process-Critical Materials. More research is required into impurity specification requirements for materials such as copper-plating solutions, CMP slurries, chemical vapor deposition (CVD) precursors, and high- and low-k materials. Particle levels per volume have been held at critical particle size; at a 1/x³ defect-size distribution, this means a cleanliness improvement of ~2x per generation.

Ultrapure Water. The 2001 WECC section of the roadmap contains an extensive discussion of ultrapure water (UPW) requirements. UPW is generally considered to have >18.1 MW resistivity and <1 ppb in ionics (cations, anions, metals), total organic carbon (TOC), silica (dissolved and colloidal), particles, and bacteria. Although criteria exceeding the present state of the art have not been projected, individual manufacturers can establish them as needed. An important trend in the UPW area is the categorization of some parameters as process variables rather than contaminants, depending on whether the criterion is stability or absolute levels. For example, some semiconductor manufacturers treat dissolved oxygen as a process variable, while others still consider it a contaminant. Stability of temperature and pressure are also becoming more important. A list of UPW parameters, measurement locations, and test methods is presented in Table VI.

Parameter Measured (POD/POC)a Test Method Resistivity On-line Electric cell Viable bacteria Lab Incubation EPI bacteria Lab Stained samples with fluorescent microscopy Scan RDI Lab Laser scanning cytometry Reactive silica On-line or lab Colormetric Colloidal silica Calculation Total minus reactive Total silica Lab ICP-MS Particle monitoring On-line Light scatter Particle count Lab SEM—capture filter at various pore sizes Cations, anions, metals Lab Ion chromatography, ICP-MS Dissolved O2 On-line Electric cell TOC On-line Resistivity/CO2 aPOD = point of distribution; POC = point of connection

Table VI: Parameters and test methods for ultrapure water.

Key Challenge. The most critical challenge facing the WECC has remained unchanged since the publication of the last two roadmaps: the need for test structures and advanced modeling to determine the effects of trace impurities on device performance, reliability, and yield. Without such correlations, it is very difficult to predict the need for increasing levels of process material purity. Without such predictions, semiconductor manufacturers run the risk of not having the right materials and distribution systems in conjunction with new processes and products. Generally speaking, the lack of clear correlations between impurity levels and device performance has led either to a direct relaxation of material impurity requirements or the postponement of possible improvements.

Conclusion

During the deliberations of the yield enhancement working group that resulted in the 2001 ITRS Yield Enhancement chapter, some key themes emerged. First and foremost, although some inspection tools for high-aspect-ratio structures exist, they do not meet projected throughput, sensitivity, and cost-of-ownership requirements. Inspection capability is critical to yield learning and process control in current and future technology nodes. Bridging the current gap will require that manufacturers of inspection tools make significant R&D investments.

The development, advancement, and commercialization of integrated data management capabilities to accelerate yield learning from the introduction of process technology through product maturity is crucial to driving rapid yield ramps. IDM must take into consideration circuit design, visible and nonvisual defects, parametric data, and electrical test information to recognize process trends and facilitate rapid root-cause identification of yield-loss mechanisms, thereby limiting the impact of excursions on the manufacturing line. Sourcing nondetectable defects, parametric problems, and electrical faults by acquiring a deeper understanding of design-to-process interactions will become just as critical as sourcing visible defects.

A lack of clear correlation between airborne and liquid impurity levels and their impact on device performance has made it difficult to determine actual contamination requirements in the immediate wafer environment. A focus on the development of test structures and advanced modeling techniques is required to determine if technology requirements should be tightened in future iterations of the roadmap.

Finally, ongoing validation of particles-per-wafer-pass and process-induced defect budgets for tools is required. The continued development of yield-loss modeling capabilities (for parametric-, systematic-, and circuit-limited yields) is required to meet ramp yield targets on products at current and future technology nodes.

Acknowledgments

The authors wish to acknowledge the significant contributions of the members of the technology working group who participated in the development of the Yield Enhancement chapter of the roadmap: Bob Bryant, Scott Buck, Dave Chamness, Jeff Chapman, Darren Dance, Dianne Dougherty, Mel Effron, Warren Evans, William Fil, Lothar Fitzner, Walt Gardner, Honey Goel, Christine Gombar, David Jensen, Paul Jones, Dan Maynard, James McAndrew, Toshihiko Osada, Michael Patterson, Ralph Richardson, Josh Shenk, Ken Tobin, and Hank Walker.