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MicroMagazine.com

Technical Viewpoint

Improving cost of ownership and performance of CMP process and consumables

Karey Holland, Ann Hurst, and Harvey Pinder

Technologists and scientists working on chemical-mechanical planarization (CMP) have improved the technology's cost of ownership (COO) since it was first introduced into semiconductor chip manufacturing in the late 1980s. In conjunction with enhancements in the fields of lithography, reactive ion etch (RIE), and chemical vapor deposition (CVD), CMP promised to reduce defectivity while improving productivity through global planarization. That potential advantage meant that higher-than-desired costs might be tolerated in order to reap the benefits. However, the honeymoon is over. Manufacturers expect to enjoy the promised integration advantages of CMP but with a COO that compares favorably with that of other key semiconductor processes.

After briefly reviewing the motivation for CMP in the user community, this article addresses current and future cost-of-ownership improvements.

Advantages of Using CMP

It is ironic that a process most engineers scoffed at 15 years ago ("You're going to put WHAT on my wafer?") has actually decreased defectivity rather than raised it. The presumed mechanism for this improvement is that defects—in oxide dielectric, for example—were knocked down or removed altogether. Yield losses caused by line-to-line shorting actually decreased after the advent of CMP. The fear of leaving embedded slurry residue on the wafer did not materialize. To the contrary, the use of CMP has led to fewer significant and yield-detracting defects on the wafer surface than was previously the case. Figure 1 shows typical data from good test wafers that had been processed on a Mirra Mesa polisher from Applied Materials (Santa Clara, CA) using a 711 hard porous pad from Thomas West (Sunnyvale, CA) and 2585 slurry from Cabot (Aurora, IL). The data demonstrate that defect counts generally decreased after tungsten CMP and a post-CMP clean were performed.

Figure 1: Defect count change after tungsten CMP and post-CMP clean.

Without CMP, the significant topography of oxide deposited on a metal 1 layer would worsen in subsequent metal layers. In many subsequent process steps, reducing that topography would represent a severe technical challenge. First and foremost, lithography would be affected. Modern step-and-repeat lithography has very tight tolerances for depth of focus. In fact, depth of focus is not much greater than the thickness of the resist spun onto a planar wafer. Resist deposited on a layer with significant topography could be two times thicker than a standard resist film. Achieving straight profile images in a thicker film might be impossible. Moreover, reflectivity over metal-covered steps compounds the challenge. Fortunately, those problems are much less likely to occur on films that have been polished flat.

Reactive ion etching of films that traverse topography poses an additional challenge. The nonuniformity of the metal films and resist-patterning layer resulting from topography make it extremely challenging to perform across-the-wafer RIE to produce uniform images. On planar surfaces, however, performing RIE is not difficult. Furthermore, a CVD dielectric engineer, while always striving for across-the-wafer deposition uniformity, rests easier knowing that the next process step—CMP—will correct any deposition nonuniformities.

CMP smooths the integration of other process modules. Thus, it is no wonder that the process has developed despite a relatively high COO: the yield improvement with CMP could "buy" any improvement costs, and the goal was getting the process into manufacturing immediately.

Because CMP offers a wide range of advantages, attitudes toward it have changed. As it has become a mainstream process, device manufacturers have found and continue to find new and wonderful applications for it. Accordingly, manufacturing an integrated circuit may now require in excess of 10 iterations, which, in turn, has increased the technology's cost of ownership. COO is a function of many factors, but it is the equipment and consumables above all that make CMP so expensive.

CMP Then and Now

In the early days of CMP, polishing tools were stand-alone systems with wet-out configurations in which polished wafers were transferred to wafer boats submerged in water. Dripping wet boats of wafers were removed from CMP tools and manually transferred to wet-in, dry-out post-CMP cleaners. This process increased cycle times and was inherently undesirable (dripping water and slurry on the floor is not good for fab cleanliness, let alone safety).

Now, CMP tool sets have integrated post-CMP cleaners, so that wafers are cleaned in a dry-in, dry-out process. These cleaners are more efficient than the old wet-out systems, ensuring that slurry removal and drying take place consistently, with virtually no impact on the cycle time of a load of wafers. Of course, the cost of CMP tools also has increased significantly. In the early 1990s, a 200-mm stand-alone CMP tool and cleaner cost under $1 million; current integrated 200-mm tools cost $2 million or more.

In the old days, test and monitor wafers were used for process qualification each time a pad was changed. A new batch of slurry was used any time the tool had been idled or just because the fab engineers didn't trust the process stability. Frequently, process adjustments had to be made after the first two monitor wafers had been processed, and then another monitor wafer had to be processed. Some fabs determined that blank monitor wafers did not test the process adequately, so actual device wafers were sent through the process, tested, and then repolished if necessary. For each of these steps, the wafer had to be polished, cleaned, and then remotely measured on a stand-alone film-thickness measurement tool. This procedure contributed to very low CMP tool utilization, driving up COO. Unfortunately, despite the use of monitor wafers and device send-ahead wafers, product wafers still ran the significant risk of being misprocessed and in need of rework.

Now, with integrated cleans and in situ film-thickness measuring, setup wafers can be processed in much less time than previously. More significantly, product lots can be monitored in real time. Feedback and feedforward loops are being instituted so that product wafers are subjected to much less risk than in the past.

Tool utilization used to be the number one COO issue for CMP. But tremendous progress has been made on that front, with some mature tool sets boasting a mean time between failures of 500 hours.

The High Cost of CMP Consumables

With such significant equipment improvements, the current COO focus has shifted to consumables. Here the issues include setup times for consumable changes and the cost of the consumables themselves. Fortunately, technologists are developing new materials that both decrease the frequency of consumable changes and substantially improve the consumables' cost per wafer processed. Furthermore, these COO improvements have been achieved while defect counts and surface contamination have declined.

Consider pad life. When pads are changed, tool utilization is strongly affected. While the process of changing pads is time-consuming, it is insignificant compared with the time it takes to break in a new pad and requalify the tool. Breaking in a pad can take nearly an hour, and when you include the cost of monitor wafers, send-aheads, and multiple process adjustments, the entire process can easily take several hours. Why does it take so long to get the process back into spec? When a traditional solid polyurethane pad is installed on the CMP platen and broken in, the removal rate can be as much as 20% higher or lower than the starting rate of the previous pad. It may take the process engineer several iterations to get the system back to specifications.

Modern manufacturing techniques produce consistent pads. Unlike traditional solid polyurethane pads, new pads are made in single-thickness sheets, where cure times and temperatures are the same for all pads. Some technologies in development produce pads that are hard enough to planarize copper and oxide topographies. Unlike polyurethane pads, which must undergo substantial surface removal between each wafer processed to maintain CMP removal rates and nonuniformity, hard pads require minimal conditioning and sustain <5% loss of thickness over a run of 1500 wafers. Consequently, such pads are stable throughout their lifetimes and can perform nearly 2000 wafer runs. Polishing more wafers per pad means fewer pad changes, lower requalification costs, decreased tool downtime, and lower COO.

New-generation pads are manufactured so that they have a highly reproducible pad surface. The result is that semiconductor manufacturers rarely need to make process adjustments when pads are changed. Additionally, using such pads reduces both requalification and wafer-monitoring times, which enables engineers to get tools back on-line quickly.

The largest contributor to CMP COO is slurry, particularly for tungsten, aluminum, and copper CMP processes. These metal slurries may be composed of abrasive particles, oxidizers, brightening agents, and other additives that are difficult to suspend. Thus, they require extensive and expensive research and development. Typical next-generation tungsten slurries cost from $20 to $70 per gallon in the United States and substantially more overseas. Unfortunately, traditional CMP tools using solid polyurethane pads use as much as 150 to 200 ml/min of slurry per wafer, and a typical tungsten polish time is 2 minutes. Moreover, most of this slurry is not actually used in the polishing process. Traditional pads made of solid polyurethane only have surface asperities and grooves to transport slurry to the wafer-pad interface, and the wafer acts like a squeegee, removing slurry from the pad. That tendency contradicts Preston's law, which states that increasing downforce or increasing pad-to-wafer velocity increases removal rates. Removal rates can actually fall as platen speeds rise because of slurry starvation at the wafer-pad interface. Very expensive slurry is spun off the pad and wasted, wafer after wafer. Figure 2, a typical cost-of-ownership breakdown for tungsten plug CMP, demonstrates that slurry expenditures represent almost 50% of all CMP-related costs.

Figure 2: Typical cost-of-ownership breakdown for tungsten plug CMP.

Although they are hard, new-generation pads also are porous and thus capture and hold the slurry, leading to more-efficient slurry use. In fact, hard porous pads use 50% (and perhaps even as little as 20%) less slurry than solid polyurethane pads, while improving removal rates and defect counts. That translates into a considerable COO savings.

Often overlooked, most notably at technical symposiums, are pad conditioners. That is unfortunate, since pad conditioners—diamond grit attached to a disk or puck—play a critical role in pad life and performance. They are overlooked because they do not touch the wafer surface. Rather, their job is to refresh the pad surface during or between each wafer polish to maintain consistent CMP removal rates and nonuniformity. Conditioners are expensive items that must be changed routinely. Indeed, their cost of ownership per wafer polished is comparable to that of the pads themselves.

In order to roughen up the surface of solid polyurethane pads so that they will hold slurry, the conditioner must be swept across the pad a number of times with a downforce of several pounds per square inch. Without substantial roughening, the pad will behave even more like a squeegee than it does after conditioning. Clearly, the roughening process wears down the pad quickly, resulting in relatively few wafer passes per pad. But the process also wears down the conditioner, leading to shortened conditioner life and increased costs.

The conditioning of new-generation pads requires much lower downforce and many fewer sweeps across the wafer than that of previous pads because the pad holds the slurry naturally and does not require substantial roughening to bring the slurry into contact with the pad. One consequence of less conditioning is longer pad life. Another is longer conditioner life. Yet another is the improved tool utilization that results from having to spend less time on conditioning and breaking in the pads. Traditional polyurethane pads must be broken in for 30–45 minutes or more before the first monitor wafer can be run, while hard porous pads require less than 10 minutes of conditioning.

Less-aggressive conditioning can lead to improved defect counts and improved COO. A large amount of a polyurethane pad is abraded by the conditioner. If any of this pad residue is not washed away, it can scratch the wafer surface. Moreover, aggressive conditioning can cause diamonds to break loose from the conditioner and become embedded in the pad—a defectivity nightmare that everyone fears.

Finally, because the pad holds slurry like a sponge, material removal rates are enhanced by high platen rotation speeds and low downforce. This parameter space is difficult to achieve with traditional solid polyurethane pads, because the hydroplaning effect that occurs can actually slow down the polishing rate. With hard porous pads, polishing rate improvements of 20% are typical. Higher removal rates result in the processing of more wafers per hour, the consumption of less slurry per wafer, and significantly lower COO.

Why It Pays to Improve CMP Consumables

It has been demonstrated that all of these improvements are possible while improving yields through decreasing postpolish defect counts, lowering polish removal rates, shrinking nonuniformity, and improving planarization. A conservative COO estimate, summarized in Figure 3, indicates that cost of ownership can be reduced by more than 33% if proper process improvements are made.

Figure 3: An improvement in the cost of ownership can be achieved by reducing slurry use and pad break-in times, as well as by extending pad lifetime.

Reducing CMP cost of ownership has followed two paths. The first has focused largely on tool reliability and process integration. The second has focused on consumables. New technology is improving tool utilization and tool throughput, extending the lifetime of pads and pad conditioners, and substantially decreasing the consumption of expensive slurry. Lowering defectivity and improving the CMP process while lowering the cost of ownership confirms the old adage that "simpler is better."



Karey Holland, PhD, is vice president of technology at Thomas West (Sunnyvale, CA). Before joining the company, she was CTO and vice president of process technology at SpeedFam-IPEC and IPEC for more than five years. Prior to that, she spent 13 years on advanced submicron CMOS devices at IBM and Motorola. Holland contributed to the interconnect technology development of the first chips to use fully planarized interlevel dielectrics and tungsten plug technology, after which she helped introduce them into manufacturing. She received a PhD in analytical chemistry from Pennsylvania State University in University Park. (Holland can be reached at 408/481-9200, ext. 119, or kholland@thomaswest.com.)
 
Ann Hurst is a member of the senior technology staff at Thomas West. Before joining the company, she was the technical manager of field process applications and a process applications engineer at SpeedFam-IPEC and IPEC. Prior to joining IPEC, she worked at Wacker Silicones in the development of slurries for the semiconductor industry. She received a BS in biological sciences from Michigan Technological University in Houghton. (Hurst can be reached at 408/481-9200 or ahurst@thomaswest.com.)
 

Harvey Pinder is a member of the senior technology staff at Thomas West. Before joining the company, he was director of Taiwan operations for SpeedFam-IPEC and general manager of IPEC's international services Taiwan branch for more than three years. Prior to joining IPEC, he worked at Intraco Taiwan Corp., Tencor, and Sematech in various semiconductor equipment service positions.
He received electronic engineering training through the U.S. Navy. (Pinder can be reached at 408/481-9200 or hpinder@thomaswest.com.)


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