The ability to achieve those ambitious surface-preparation goals hinges on the ability to combine process steps in order to minimize the number of air-liquid interfaces that the wafer experiences, which will, in turn, reduce the number of surface defects. It will also be important to combine chemical process steps with rinsing and drying operations in a single process vessel, especially in the case of hydrofluoric acid (HF)–last cleaning processes, which are becoming more widespread with the use of sub-30-Å gate oxides. Performing a true HF-last process in a single vessel will help to reduce exposure to the oxidizing ambient, achieve ideal surface passivation (i.e., hydrogen-terminated silicon), and minimize particle addition to the sensitive hydrophobic surface.

Although currently acceptable, many drying technologies, including various types of isopropyl alcohol (IPA) dryers, will be incapable of meeting the needs of future device technology nodes.² In particular, IPA dryers based on the surface-tension gradient have been identified as potentially ineffective on high-aspect-ratio features.³ Because of the Marangoni effect, the gradient may be drastically reduced when the meniscus is lost, or it may be altered when it hits deeply cut features.

This article describes drying technology based on IPA vapor condensation that was developed by SCP Global Technologies (Boise, ID) to meet both current and future rinsing and drying requirements.^4–6 The patented GreenDry process can perform the final surface-preparation clean and passivation steps using HF, hydrochloric acid (HCl), or ozone injection, followed by a DI-water rinse and the IPA vapor condensation dry, all within a single process chamber. Data from long-term testing of the technology in a Class 10 applications lab are presented, along with production data from fab installations. Additionally, production qualification data from a fab start-up are included to highlight the importance of joint process development efforts between equipment suppliers and their fab customers.

The Integrated Technology

As shown in Figure 1, the process module includes three major components: an IPA vapor generator, a quick-dump rinse tank inside the dryer enclosure, and a drain and exhaust system. A typical process sequence consists of four phases: (1) chemical processing, (2) DI-water rinsing followed by a quick dump, (3) IPA vapor condensation drying, and (4) a hot N₂ final dry. The wafers are never exposed to ambient air between these process steps.

Prior to wafer insertion, the chamber is filled with the desired chemical concentration by metering the chemical into DI water. The wafers are then inserted and subjected to an overflow process with continuous chemical injection at the desired set point. On completion of this chemical processing, the wafers are rinsed with DI water, which is subsequently dumped into a catch basin connected to the system's drain.

The dump phase takes 3–4 seconds, after which a predefined amount of IPA liquid is injected into the heated vapor generator. Heated N₂ gas carries the evaporated IPA vapor into the chamber through a distribution manifold in the lid at a well-defined flow rate and concentration. Because of the significant temperature difference between the water-coated wafers and the heated vapor, the vapor condenses at the wafer surface instantaneously upon exposure. The low surface tension of the resultant water/IPA mixture then causes the fluid to bead up and sheet off the wafer via the combined action of gravity and the continuing N₂ flow. At the end of the vapor phase, no water remains on the wafer surface, and any residual IPA evaporates during the final hot-nitrogen dry phase. This final phase is timed so that both the wafers and the cassette will emerge from the chamber completely dry.

The following sections describe the capabilities of the integrated technology used in SCP's E200 automated surface preparation systems. The E200 platform features multiple integrated processes that combine dilute chemistries with rinses, thereby enhancing process flexibility. The system also minimizes cost of ownership, since its chemical and water consumption and equipment footprint requirements are lower than those of multiple-tank solutions.

Examples of integrated processes include combined process and rinse tanks for SC-1, called the SC-1 Pro-rinse, and HF, HCl, or ozone injection into the IPA vapor–dry and other rinse tanks.^7,8 Such processes can ultimately result in optimal cleaning performance and improved device yields.⁹ Long-term characterization data obtained in the applications lab are presented below, along with data collected at several fabs. Finally, results obtained during process development at austriamicrosystems' new fab are presented.

Particle Performance Data from the Applications Lab. The particle performance of the integrated technology was characterized for both hydrophilic and hydrophobic wafer- surface conditions over a 2-year period in the Class 10 applications lab. Using an SP1/SP1-TBI system from KLA-Tencor (San Jose), particles were quantified at sizes of >0.12 µm, with a 3-mm edge exclusion, and >0.09 µm, with both 1- and 3-mm edge exclusions. Wafers with hydrophilic surfaces underwent a process sequence that included a dilute SC-1 clean (1:2:100 NH₄OH:H₂O₂:H₂O) followed by the rinse and dry process steps. (The SC-1 process was necessary to ensure the hydrophilic wafer-surface state.) In order to avoid cross-contamination between acids and bases, the SC-1 step was performed in a separate tank. Wafers with hydrophobic surfaces were subjected to a dilute HF-last processing sequence, which was of sufficient duration to strip the native silicon oxide and fully passivate the wafer surface. This step was subsequently followed by a DI-water rinse and an IPA vapor condensation dry, with all process steps performed within the same chamber.

As can be seen in Figure 2, the hydrophilic wafer surfaces were particle neutral at 0.12 µm, compared with a value of 5 particle adders for the more-challenging hydrophobic wafers. These excellent results for the hydrophobic wafers can be attributed to the integration of the HF, rinse, and dry steps as well as to the optimization of the IPA drying process.

Figure 2: Particle performance at >0.12- and >0.09-µm thresholds for hydrophilic and hydrophobic wafers. Error bars indicate one standard deviation.

Particle Performance Data from a Start-Up Fab. SCP partnered with austriamicrosystems, a mixed-signal ASIC, ASSP, and system solution provider headquartered in Graz, Austria, to develop advanced wafer-surface preparation processes for its new fab. The three-level SMIF-equipped facility features a 3700-m² cleanroom area that meets all requirements for 130-nm technology. Although the fab is designed for SMIF operations, the cleanroom operates at better than Class 10.

Figure 3 shows a particle performance histogram for two typical prediffusion tools running an advanced RCA-equivalent process at the new fab. The particle threshold for these tests was set at a relatively large diameter of 0.16 µm with a 3-mm edge exclusion. The process sequence, qualified over approximately 3 months, was DI water with O₃, dilute HF, dilute SC-1 Pro-rinse, DI water with HCl injection, and the IPA vapor condensation dry. It is evident from the figure that this process sequence is particle neutral (average = 1 particle adder, standard deviation = 12). This result is exceptionally good for a clean with an SC-2 equivalent HCl injection, which lowers the pH, thereby tending to increase surface particles because of zeta potential changes.¹⁰

Figure 3: Particle performance histogram for two wafer-surface preparation stations at a start-up fab using an advanced RCA-equivalent cleaning process. The results demonstrate the integrated technology's particle-neutral performance over a 3-month period.

Figure 4 shows a histogram of particle performance data for a similar process, but with an HF-last clean. The particle threshold for this critical clean was set to a value of 0.10 µm with a 3-mm edge exclusion. The average value for a 75-day period was zero adders, with a standard deviation of 30, which is also very good. Figure 5 shows the same data plotted as particles added versus initial starting counts. These results clearly demonstrate the effectiveness of the integrated technology with an HF-last process, regardless of the initial particle levels on the processed wafers.

Figure 4: Particle performance histogram for a wafer-surface preparation station at a start-up fab using an HF-last surface passivation process. The overall number of measurements taken was 75.

Figure 5: Particle performance plot of the data for the HF-last clean shown in Figure 4.

Particle Performance Data from Multiple Fabs. Particle data from several fabs using a variety of prediffusion cleans designed to take advantage of the integrated technology's process capabilities are summarized in Figure 6. As is commonly the case, the metrology capabilities of the fabs differed from one another and lagged behind the specifications of the ITRS, making direct comparisons impossible. However, all of the data indicate that the advanced cleaning strategies resulted in excellent particle performance.

Figure 6: Particle data from multiple fab sites employing the integrated technology in a variety of prediffusion cleaning sequences. The different particle thresholds used at the different sites make a direct comparison of these data impossible.

Water Spot Performance Characterization at the Applications Lab. Extensive characterization of the integrated technology was undertaken at the lab to determine its capabilities for drying without water spots under the most demanding conditions. Tests were conducted using wafers supplied by multiple fabs with a wide variety of process challenges. These included drying in deep trenches with hydrophilic/hydrophobic interfaces, drying on heavily doped patterned poly-Si lines adjacent to oxide regions, drying heavily doped blanket poly-Si lines prior to metal silicide deposition, and drying in active areas with severe topography and hydrophilic/hydrophobic interfaces.

In one experiment, a deep trench structure with a high (40:1) aspect ratio and oxide and nitride layers was used to evaluate drying performance. This feature presented a severe drying challenge because it had a hydrophilic/hydrophobic interface at the top of the 0.19 x 7.5-µm trench, which acts in combination with surface tension effects to trap water in the trench. Figure 7 shows atomic force microscopy images of the wafer after an HF-last process, which reveal that no water spots had formed. Such spots would be indicated by the presence of silicide precipitates at the trench mouths. Further evaluation using optical microscopy confirmed these results. In contrast, when the HF-last process was performed in a typical spin rinse dryer, a large water spot could be clearly seen.

The water spot performance of the integrated technology was also evaluated using a film adhesion test. In that experiment, a heavily doped poly-Si film was cleaned with an HF-last process. The purpose of this clean was to strip the native oxide and create a hydrogen-terminated silicon surface to promote optimal film bonding and stoichiometry of the subsequent tungsten film. The process is especially challenging because of the propensity of heavily doped poly-Si to regrow native oxide if the clean is not optimal and water spotting occurs. The presence of such regrowth, which will affect the adhesiveness of the WSi_x film layer, can be determined with a standard tape test. In the case of the applications lab testing, none of the WSi layer came off when the tape was removed, indicating the absence of water spots on the processed wafers.

Additional water spot testing was performed using heavily doped patterned poly-Si lines with hydrophilic/hydrophobic interfaces. These wafers underwent an HF-last process for native oxide removal and were subsequently evaluated with an in-line scanning electron microscope. Figure 8 demonstrates that no water spots were formed on this type of test structure, which had posed repeated difficulties for the fab that supplied the test wafers.

Figure 8: SEM image of an HF-last clean on patterned poly-Si lines showing no water spots.

Water Spot Testing at a Start-Up Fab. To evaluate the integrated technology's effectiveness on active areas with field oxide edges, test wafers were processed at the start-up fab through field oxidation and nitride strip. The remaining base oxide over the active areas was then etched away using a buffered oxide etch. Hydrogen termination over the active areas was accomplished with diluted HF injection. The process sequence used in the multipurpose module was as follows: buffered oxide etchant (BOE), rinse, dilute SC-1 Pro-Rinse, DI water with HCl injection, and the IPA vapor condensation dry with dilute HF injection. Optical inspection and particle analysis results revealed a complete absence of water spots. In fact, the wafer maps showed that the process sequence was particle neutral, which is in agreement with the particle performance data from daily monitoring shown in Figure 5. In the case of one structure that was considered difficult to clean because of its hydrophobic/hydrophilic interfaces, the wafer map showed only one defect, which was found to be of unrelated origin.

Characterizing a Photoresist Wafer-Drying Process at the Applications Lab. It is becoming increasingly common for advanced process integration schemes to include a wet chemical treatment performed with patterned photoresist on the wafer. One example is a dual-gate process in which devices with two different gate-oxide thicknesses are fabricated by performing a wet etchback through a photoresist mask.¹¹ The ability to perform this etch without degrading the photoresist integrity or profile is critical to ensuring device yield, but it has traditionally posed a serious challenge for tools with IPA dryers, especially dryers with boiling-sump designs.

The ability of the integrated drying technology to process photoresist wafers was thoroughly tested using a variety of fab-supplied wafers. In one test, photoresist-patterned wafers were prepared at a fab using oxide wafers coated with 9000-Å i-line photoresist baked at 90°C for 60 seconds. In the applications lab testing, these wafers were etched in 100:1 HF for 200 seconds to achieve a 100-Å etch, then rinsed and dried using the IPA vapor condensation process. Postprocessing metrology included patterned-wafer defect analysis, optical microscopy, and in-line SEM imaging.

Wafer mapping and microscopy results demonstrated that the patterned photoresist wafer dried without water spots. Furthermore, there was no degradation or undercutting of the resist. These results were confirmed by SEM measurements of critical dimensions. Special drying recipes were developed to ensure damage-free resist processing. Depending on the sensitivity of a resist to solvent degradation, either a low-IPA recipe (<7 ml) or an optimized no-IPA recipe could be selected. Both have demonstrated excellent results, as shown by the wafer maps in Figure 9.

Implementing a Photoresist Wafer-Drying Process at a Start-Up Fab. A wet-etch process is used on resist-patterned wafers for capacitor definition in a BiCMOS process at the start-up fab. After the poly 1 gate is structured, a source drain is formed and an oxide layer is deposited via a CVD process. A photomask is then applied before the wet etch. This mask is open only over the poly 1 capacitor plates, and the open areas are selectively etched down to the poly 1 plates with BOE. The sequence performed in the integrated chamber is BOE, DI-water rinse with megasonics, and the IPA vapor condensation dry. In process qualification testing using a low-IPA recipe and a hot N₂ dry only, no evidence of resist degradation was detected. The addition of megasonics to the rinse step was shown to significantly reduce particle counts. The fab opted to use the low-IPA recipe because it facilitated process control.

Metal Contamination Performance. Researchers at the applications lab also investigated the performance of the integrated technology when a final metal contamination-removal step preceded the rinse and dry sequence. It was proposed that an injection of dilute HCl in DI water be used in place of the traditional SC-2 clean for such applications.¹² Extensive testing was performed at the lab to optimize both the metal-removal capability and particle performance of ambient-temperature HCl processes. Table I presents test results that show copper removal efficiency as a function of HCl concentration for an ambient-temperature process on intentionally contaminated challenge wafers, as measured by total reflection x-ray fluorescence (TXRF). Table II shows typical levels for all metal elements after an HF-last process, as measured by vapor-phase-decomposition inductively coupled plasma-mass spectrometry (VPD ICP-MS). It is evident from these results that dilute HCl is very effective at metal removal, even at very low chemical concentrations at ambient process temperatures.

Conclusion

Excellent process performance has been demonstrated for a novel IPA vapor condensation dryer that is fully integrated with rinsing and chemical process capabilities. The integrated technology meets the requirements of advanced processes such as ultrathin gate dielectric surface preparation, processes incorporating a wet etchback through a photoresist mask, and water spot–free processing of devices with high-aspect-ratio features. Particle and water spot data from several fab sites, including a start-up, have been similar to those obtained in the system developer's applications lab over a 2-year period, confirming that the technology can meet the ITRS goals for 130-nm and sub-130-nm processing.

References

1. The International Technology Roadmap for Semiconductors (San Jose: Semiconductor Industry Association, 2001), 16.