The development also means that work on advanced low-k materials at the 65-nm node can be transferred from 200-mm wafers to their larger counterparts. The baseline process will allow Sematech "to generate the data that help our member companies and the industry make informed decisions about their next low-k materials," says Navjot Chhabra, Sematech's director of interconnect.

The December announcement came six months after Sematech qualified process flow on 200-mm wafers and two months after qualifying silicon dioxide flow for 300-mm wafers. The 300-mm material is a methyl silicate­based dielectric with a constant of approximately 2.2. The baseline dual-damascene process uses both standard copper electroplating and CMP. Equipment manufacturers supplying the technologies are Applied Materials, JSR, Novellus Systems, SEZ, and TEL.

Toshiba to build two fabs

Looking to bolster its position in two market segments, Toshiba plans to build 300-mm fabs at two of the company's sites in Japan. The four-year expansion is expected to cost approximately $2.9 billion. The chipmaker will place one plant at Oita Operations, which makes system LSI chips for broadband networks. The other fab at Yokkaichi Operations will manufacture NAND-type flash memories. The Oita facility eventually will adopt 45-nm process technology. Construction is scheduled to begin in FY03 for mass production that is set for the following fiscal year. The Yokkaichi plant is scheduled to begin production in FY06.