Replacing piranha cleans with an O₂ RIE/fluorine process to remove post-ion-implant residues

Sam Q. Gu, Susan Allen, Chris Bowker, and Bruce Whitefield, LSI Logic; and Han Xu and Richard L. Bersin, Ulvac Technologies

Ion implantation through resist-coated silicon wafers is used to control doping levels in integrated-circuit fabrication. However, high-current or high-energy implant ions can sputter silicon or silicon dioxide (SiO₂) from the wafer substrate and deposit residues on top of the resist. In addition, implant species can penetrate into the resist, causing the formation of a resist crust and other residues. Therefore, following ion implantation, the resist should be removed, leaving the wafer surface residue-free.

Typically, oxygen plasma and a piranha wet-clean application, a mixture of sulfuric acid (H₂SO₄) with either hydrogen peroxide (H₂O₂) or ozone (O₃), are used to remove the resist. However, while oxygen plasma can ash the carbon and hydrogen components in the resist, it does not remove all inorganic residues from the wafer surface. Piranha wet cleans, which have conventionally been used to ensure the total removal of organic residues from the wafer surface, can remove some carbon and hydrogen, but they do not strip inorganic residues effectively. Moreover, the piranha process is costly and hazardous.

The veil of inorganic residue (implant species, silicon, SiO₂, and additives in the resist) often remaining on the wafer after oxygen ashing and a piranha clean would affect subsequent implant steps and must be stripped prior to further wafer processing. While additional wet chemistries such as SC-1 (NH₄OH:H₂O₂:H₂O) or diluted hydrofluoric acid (HF) can be used to remove these residues, they are costly.

This article focuses on a program initiated at LSI Logic (Gresham, OR) to evaluate an alternate technology combining dry plasma processing and simple DI-water rinses in a conventional spin rinse-dryer. The technology combines an O₂ reactive ion etch (RIE) process to remove resist crust and the addition of fluorine to a downstream oxygen plasma to remove residues. Since the removal of post-high-dose ion implantation residues is the most difficult front-end-of-line (FEOL) strip-clean process that uses piranha chemistry, it was the first process to be examined for this study. The article also highlights the cost savings that can be achieved by eliminating piranha chemistry in high-density-implanted (HDI) and other FEOL resist strip and cleaning processes. Finally, it discusses methods for monitoring and minimizing oxide loss resulting from the use of a fluorine plasma.

Figure 1: Schematic diagram of the microwave downstream and RIE stripping chamber.

Removing Resist Crust and Residues

The study presented here used an Enviro II plasma asher from Ulvac (Methuen, MA), in which process gases (O₂ combined with N₂:H₂) pass through a quartz or sapphire applicator tube that is microwave-excited to create generous concentrations of ion species and neutral free radicals. These ion species and free radicals are then injected into the chamber through a gas-distribution structure. Because the tool uses a remote plasma generated away from the wafer, as illustrated in Figure 1, the lifetime of the charged species is much shorter than that of the neutrals, causing most charged species to recombine before reaching the wafer.¹ That reaction minimizes the plasma charge contribution from the charged species. To activate the neutral oxygen reaction with resist, the wafer is heated to an elevated temperature (>230°C) by resting on top of a heated chuck. If needed, RF power can be applied to the bottom electrode, inducing physical sputtering.

Figure 2: Schematic diagram of a postimplant resist profile depicting how implant species can penetrate into the resist, driving out hydrogen to form a crust of hardened carbonized resist.

Resist is most difficult to strip after high-dose implantation because implant species, as depicted in Figure 2, can penetrate into the resist, driving out hydrogen to form a crust of hardened, carbonized resist.² If a conventional high-temperature ashing process is employed, the heating of the damaged resist results in volatilization of resist solvent trapped underneath the crust layer, which builds up pressure and causes the carbonized crust layer to rupture, or "pop." As shown in Figure 3, the piranha process frequently cannot remove debris or particles from the crust layer. In contrast, the O₂ RIE plasma used as a first step in the Enviro resist-strip system quickly removes the carbonized crust layer without heating, thereby preventing resist popping.

Figure 3: SEM image showing a popped carbonized crust layer following a piranha clean. The piranha process frequently cannot remove such debris or particles.

Oxygen plasma can convert carbon and hydrogen into CO₂ and H₂O. Combining O₂ with the forming gas N₂:H₂ generates OH species, which can convert some implant elements into volatile materials, but that combination cannot remove all inorganic residues. As shown in Table I, ashing residues composed of silicon, SiO₂, implant species (e.g., arsenic, phosphorus, or boron), carbon, and resist additives (e.g., sodium) remain on top of the wafer after O₂/N₂:H₂ ashing.³ While a piranha wet clean can reduce those surface-residue levels, it leaves behind significant amounts of residue, as indicated by the SIMS-analysis data shown in Table I. Figure 4a shows a scanning electron microscopy (SEM) image of implant residue left on a phosphorus-implanted resist wafer after O₂/N₂:H₂ ashing and a piranha clean.

To overcome that limitation, the investigators turned to a fluorine chemistry. The addition of CF₄ to O₂/N₂:H₂ plasma can generate free fluorine and hydrogen fluoride species. Both fluorine and hydrogen fluoride convert the residue into water-soluble materials. In addition, fluorine can etch SiO₂ underneath the residue, which may loosen residue attached to the wafer.

Figure 4: SEM image of phosphorus implant resist wafer after (a) O2/N2:H2 MW ashing and a piranha clean, and (b) O2/N2:H2 ashing combined with a CF4/O2/N2:H2 plasma clean and a DI-water rinse.

By switching to a CF₄/O₂/N₂:H₂ cleaning process, a 200-mm fab running a 0.25-µm technology with 10,000 wafer starts per week can reduce its annual consumption of H₂SO₄, H₂O₂, and DI water by 66,560, 6240, and 1,144,000 gallons, respectively. It can also reduce costs associated with storing, handling, distributing, and disposing of the hazardous and corrosive chemicals, achieving a yearly savings of more than $500,000. Fabs running 0.18-µm and smaller technologies can achieve even greater cost savings, since smaller devices with more front-end layers require more processing than larger ones.

Monitoring and Minimizing Oxide Loss

Fluorine plasma is very effective at removing ion implant residue, but it can also attack SiO₂ on wafer areas where no resist or residue is present. As device dimensions shrink, maintaining oxide thickness is very critical for front-end processing. For example, if fluorine attacks field oxide too excessively, the field oxide can become recessed deep near the island edge. Contacts that overlap field oxide can reach wells, leading to junction leakage. Since modern devices may have more than 10 implant layers, even small amounts of oxide loss per layer can result in an accumulated total loss that can seriously lower device performance. Therefore, monitoring oxide loss and minimizing fluorine's effect on SiO₂ during resist cleaning are critical.

Figure 5: Oxide thickness changes on bare silicon wafers that underwent an O2/N2:H2 MW downstream clean, an O2 RIE clean, or a CF4/O2/N2:H2 MW downstream clean.

In order to accurately measure small amounts of oxide loss in front-end strip-and-clean processing using fluorine chemistry, thin thermal oxide wafers are typically used as monitor wafers. However, when such wafers are exposed to oxygen plasma, oxygen can penetrate through the SiO₂ and oxidize the underlying silicon substrate, artificially increasing SiO₂ thickness. To study the oxide film thickness changes, experiments were conducted under three different plasma conditions: O₂/N₂:H₂ microwave (MW) downstream plasma, O₂ RIE plasma, and CF₄/O₂/ N₂:H₂ MW plasma. Wafers were run multiple times through the same plasma.

Film-Thickness Changes on Wafers with 11-Å-Thick Native Oxide. In the first series of tests, bare silicon-substrate wafers with a native oxide thickness of ~11 Å were used. As detailed in Figure 5, the oxide thickness under O₂/N₂:H₂ MW downstream plasma conditions grew to ~18 Å after the first exposure to the plasma. It increased slightly with additional plasma exposures and finally stabilized at ~20 Å. Thermal diffusion is this plasma condition's main oxidation mechanism; as the oxide layer grows thicker, less oxygen can reach the silicon substrate, decreasing the film's growth rate despite additional plasma exposures.

In contrast, under O₂ RIE plasma conditions, oxygen ions also have kinetic energy when they reach the wafer surface and can penetrate deep into the substrate. After the first exposure to O₂ RIE plasma, the oxide thickness jumped from 11 to 60 Å. The oxide thickness continued to grow with additional plasma exposures and reached >90 Å after five runs.

The CF₄/O₂/N₂:H₂ MW plasma promotes faster oxide growth than O₂/N₂:H₂ MW plasma because of fluorine's ability to enhance oxygen diffusion through the oxide layer. Oxide film thickness under CF₄/O₂/N₂:H₂ plasma conditions grew from 11 to 25 Å after the first run, and continued to increase in thickness up to 40 Å. As the fluorine plasma etched the oxide film, oxygen diffused through the oxide and oxidized the silicon substrate. After three plasma exposures, oxide growth stabilized, suggesting that oxide wafers with an initial thickness of <40 Å are not sufficient for monitoring oxide loss in a CF₄/O₂/N₂:H₂ plasma process.

Plasma Treatment Preplasma Height (Å) Postplasma Height (Å) Difference between Post- and Preplasma Height (Å) O2/N2:H2 MW downstream plasma 2.02 1.83 –0.19 O2 RIE plasma 2.13 1.76 –0.37 CF4/O2/N2:H2 MW plasma 2.14 1.83 –0.31

Table II: Wafer surface roughness (root-mean-square height) as measured by atomic force microscopy.

AFM measurements demonstrate that wafer-surface roughness improved slightly under all three plasma conditions, as illustrated in Table II.

Film-Thickness Changes on Wafers with 90- or 300-Å-Thick Native Oxide. Figure 6 shows oxide film thickness changes for wafers with an initial oxide film thickness of ~90 or ~300 Å. Under O₂/N₂:H₂ MW plasma conditions, these wafers did not experience a change in native oxide thickness, since oxygen radicals can only diffuse <90 Å in thermal oxide at ~230°C.

Under O₂ RIE conditions, on the other hand, oxide thickness only stabilized at 320 Å (as shown in Figure 6b), since oxygen ions in RIE can penetrate ~300 Å in thermal oxide.

Figure 6: Oxide thickness changes on bare silicon wafers that underwent an O2/N2:H2 MW downstream clean, an O2 RIE clean, or a CF4/O2/N2:H2 MW downstream clean. Initial oxide thickness was (a) ~90 Å, and (b) ~300 Å.

Under CF₄/O₂/N₂:H₂ MW plasma conditions,the oxide thickness on wafers with either a 90- or 300-Å-thick native oxide layer decreased ~6 Å per run. The slope of the oxide loss decreased as the oxide thickness decreased below 65 Å, as illustrated in Figure 6a. These results indicate that the minimum oxide thickness should be >65 Å in order to derive reliable oxide-loss data from CF₄/O₂/N₂:H₂ MW plasma and to prevent oxide growth, as discussed above.

Figure 7: Impact of increasing chuck temperature, MW power, N2:H2 forming-gas flow, and CF4 flow on oxide loss when using CF4/O2/N2:H2 MW plasma.

Process Parameter Experiments. To study the effects of process parameters on oxide loss when using CF₄/O₂/N₂:H₂ MW plasma, a design of experiment was conducted. Figure 7 shows the impact of each parameter on oxide loss. The experiment demonstrated that raising the chuck temperature and MW power slightly increases oxide loss, which results from the increase in thermal activation and CF₄ dissociation. Increasing the flow of the N₂:H₂ forming gas slightly decreases oxide loss. However, CF₄ flow has the most significant impact on oxide loss. While decreasing CF₄ flow reduces oxide loss, it also reduces the efficiency of the residue-stripping process. Therefore, CF₄ flow must be adjusted to achieve a balance between acceptable oxide loss and residue-stripping efficiency.

Conclusion

Plasma wafer-cleaning processes for post-HDI and other FEOL layers have been successfully developed and qualified for IC manufacturing. By adding fluorine to resist stripping chemistry, a piranha wet cleaning step can be replaced with a simple DI-water rinse. Plasma clean processes have the same or better residue-removal effectiveness and sort yields than piranha cleans. However, when using fluorine chemistry, reliable oxide-loss monitoring must be conducted. This study indicated that oxide monitor wafers must have an initial film thickness >90 Å. In addition to its applicability in FEOL applications, the plasma process can also be used in back-end-of-line processing to completely replace the use of costly and hazardous chemical solvents for postvia etch cleaning.⁴

A significant reduction in wet-chemical use by the semiconductor industry can contribute greatly to reducing the environmental impact of wafer manufacturing, the hazards faced by cleanroom workers, and the direct manufacturing costs of IC devices. Countries developing significant chipmaking capacity, such as China, Singapore, and India, can lessen the environmental impact of the manufacturing process and substantially reduce the infrastructure costs associated with handling and disposing of hazardous chemical wastes by lowering wet-chemical consumption. Fabs in those countries can expand wafer production per square foot of cleanroom by reducing the amount of space they dedicate to costly and large wet processing stations.

Acknowledgments

This article is a revised and expanded version of a paper presented at the Electrochemical Society International Semiconductor Technology Conference, Shanghai, May 27–30, 2001. Used with permission.

References

1. J Shi et al., "Damage Reduction in Dry Resist Stripping Systems," Solid State Technology 38, no. 10 (1995): 75–82.

2. Y Okuyama, T Hashimoto, and T Koguchi, "High Dose Ion-Implantation into Photoresist," Journal of the Electrochemical Society 125, no. 8, A (1978): 1293–1298.

3. D Flamm, "Dry Plasma Resist Stripping. Part II: Physical Processes," Solid State Technology 35, no. 9 (1992): 43–48.

4. D Dopp et al., "Manufacturing Qualification of an All-Dry Via DeVeil Plasma Process" (paper presented at the Third International Symposium on Environmental Issues with Materials and Processes for the Electronics Semiconductor Industries, Toronto, May 14–18, 2000).

---

Sam Q. Gu, PhD, is a staff process development engineer at LSI Logic (Gresham, OR) with more than 10 years of experience in semiconductor research, process development, and integration. Gu is a member of the Electrochemical Society and holds patents in optical amplifier, plasma etch, and semiconductor process integration. He received a BS in condensed matter physics from Nanjing University in China and a PhD in solid-state physics from the University of Utah in Salt Lake City. (Gu can be reached at 503/618-3634 or sgu@lsil.com.)

Susan Allen is an etch ash and clean process engineer at LSI Logic in Gresham, OR. The coauthor of one article in the field of semiconductor manufacturing, she received a BS in chemical engineering from Oregon State University (Corvallis) in 1999. (Allen can be reached at 503/618-4578 or sbjorklu@lsil.com.)

Chris Bowker is a process engineering manager at LSI Logic in Gresham, OR. He has 23 years of experience in the semiconductor industry in both process development and manufacturing capacities. Bowker holds a patent in plasma etching and has authored or coauthored several papers on plasma fault detection techniques. He received a BS in physics from the University of Colorado in Boulder. (Bowker can be reached at 503/618-4580 or cbowker@lsil.com.)

Bruce Whitefield is director of engineering at LSI Logic in Gresham, OR. With 24 years of experience in the semiconductor industry, including in fab and assembly operations, he holds patents in the areas of plasma etch and optical proximity correction, yield analysis methods, statistical postprocessing, and manufacturing data systems. He received a BS in chemical engineering from Oregon State University in Corvallis. (Whitefield can be reached at 503/618-4656 or brucew@lsil.com.)

Han Xu, PhD, is director of process technology at Ulvac Technologies in Methuen, MA. He joined the company as a staff process engineer in 1994. Previously, he performed postdoctoral research on gas-phase silicon wafer cleaning at the Massachusetts Institute of Technology and surface chemistry and analysis at Harvard University in Cambridge, MA. Xu holds several patents in the field of silicon wafer processing and has coauthored more than 30 technical papers and presentations on silicon processing and surface science. He is a member of the American Vacuum Society and the Electrochemical Society. He received a PhD in physical chemistry from the University of Washington in Seattle. (Xu can be reached at 978/689-6333 or hxu@ulvac.com.)

Richard L. Bersin was a senior technical staff member at Ulvac Technologies until his retirement in mid-2002. He joined the company in 1992 after three years at Ulvac Japan. In 1969 he founded International Plasma, which specialized in low-temperature ashers for photoresist stripping. At that time, he coinvented the etch-tunnel, the Faraday-cage configuration for enhancing the performance of barrel ashers and etchers. Bersin holds more than 12 patents, many of which are in the fields of plasma ashing, etching, and equipment design. He is a member of IEEE, the American Vacuum Society, the Electrochemical Society, SEMI, and other organizations. He received a BS in nuclear physics from the Massachusetts Institute of Technology in Cambridge and an MS in mathematical physics from Northeastern University in Boston. (Bersin can be reached at 978/887-6952 or dickbersin@mindspring.com.)