ILLUSTRATION BY JAMES SCHLESINGER

The latest update of the International Technology Roadmap for Semiconductors has yielded to the effects of the semiconductor industry's worst recession ever. For the first time, the revised roadmap contains no forecasts for the introduction of new technologies. The 2002 ITRS Update retains the table headings, technology characteristics tables, and timing of the 2001 version.

The 1999 ITRS first warned of a "red-brick wall" at the 100-nm technology node, so called because the color red is used to indicate that no solutions exist to continue transistor scaling in accordance with Moore's law. However, the 2002 update sees the semiconductor industry finding solutions to the roadblocks at the 100-nm node by 2003 instead of 2005, as predicted in the 2001 ITRS.

The industry's health will affect the major rewrite now under way for the ITRS. The complete makeover is due by December 2003, and the revision will show whether the progress made toward 90-nm processing claimed by some chipmakers is a trend or a "just a moment of reflection," as the authors write in the foreword to the 2002 update.

The update does contain revisions in all chapters. More than 100 tables have been changed, and line items have been changed to correlate with other chapters. In addition, new line items were added to some tables to show a change in the difficulty of meeting a specific technological challenge. Those changes are shown by a color change in the cell. Tables with updates are shown with a line-item comparison of the 2001 Roadmap and the word was and the 2002 version with the word is.

A new category, titled "Interim Solutions Are Known," has been added to the legend in the table of requirements. A new cell color is used in revised tables for lithography, interconnect, metrology, and modeling and simulation. The color for the interim solutions category is a variegated colored cell with a red tag.

"It looks like we're good using the present pace of the roadmap until about 2005," says Alan Allan, an Intel staff engineer reporting to the ITRS chairman, Paolo Gargini. By mid-decade, though, "historical trends diverge. That's why you hear all this debate and discussion."

That discussion encompasses issues such as the introduction of new materials for enhancing gate performance and improving the storage performance of DRAMs, Allan says. In the short term, CD control for lithography is acceptable for microprocessors with "workarounds" available.

In the key area of defect reduction, "the biggest challenge is, of course, in modeling; to feel that they really have a good robust model of the true defect measurement in the future," Allan says. Chipmakers "are very challenged by the continued shrinking of the cell sizes and transistor sizes that is forecast in the roadmap. They especially have to watch the active areas."

Christopher Long, cochairman of the yield enhancement international technology working group, sees no substantive changes in the technology focus of his group. The advisory engineer with IBM Microelectronics says that high-aspect ratio inspection (HARI)—pinpointed in the 2001 ITRS—still remains a high priority.

"I haven't seen anything yet that is significantly different from 2001," Long notes. "One thing that we're really focusing on is wafer-environment contamination control. We ramped up that whole section."

Long says that smaller dimensions will push ever-more-stringent requirements for gases, chemicals, and DI water "so that we won't see yield impact or reliability impacts. Wrapped up in that also are the looming airborne contamination issues—what levels [or contaminants] do we need to be at with critical linewidths?" Long says "a big team" of more than 20 members is focusing intently on wafer-environment contamination control.

In the critical metrology area, requirements for CD measurement "were made tighter by the need to carefully monitor the lithography process separately from etch," notes Alain Diebold of the metrology working group. He says that the lithography technology working group has approved off-line measurements for line edge roughness.

"I expect that for etch it will turn into linewidth roughness for control of transistors and line edge roughness at the printed gate for photoresist for controlling just the lithography process itself," Diebold says. That is a change from the 2001 update, and he believes the change will make it into the 2003 rewritten document.

"Other than that," Diebold notes, "in 2002, a few things that were in the interconnect area have gone from red to yellow, because there's a potential solution out there." One example is finding voids in copper. "People can determine pore size in low-k materials by x-ray method or by ellipsometric pore symmetry."

Allan insists that the industry should be ready to tackle the 90-nm technology node by 2004. DRAM manufacturers "and even Toshiba, the system-on-a-chip people, have announced pushes." He also notes that dynamic RAM half-pitch—the "leading-edge roadmap characteristic"—is set to "go below 100 nm in 2003."

Allan notes that gate lengths, as shown "in the graphs on the report, have accelerated faster than fundamental half-pitch to meet aggressive performance requirements that actually passed under the 100-nm level in 1999. So, we passed into the nanometer dimension three years ago."

The 2002 ITRS Update is available at http://public.itrs.net.