Integrating an H₂O vapor step into postetch residue removal processes

Carlo Waldfried, Roger Sonnemans, Orlando Escorcia, and Ivan L. Berry, Axcelis Technologies; and Abbas Rastegar and Marcel Broekaart, Philips Semiconductors

At advanced technology nodes, postetch polymer removal is a critical step in the IC manufacturing process, especially when materials such as low-k dielectrics are involved. With aluminum interconnect technology, vertical via holes are etched into the intermetal dielectric to link etched metal lines from different layers of the interconnect structure. To obtain nearly vertical profiles for the via sidewalls, fluorocarbon chemistries are used to create a protective layer during the etch process. While all of this protective layer would be removed by the end of the etch process in an ideal situation, in reality this is not the case. Therefore, a postetch cleaning step is required to remove residual polymer, which could lead to high-resistance or nonconductive vias. Polymer residues on the sidewalls of metal line structures also must be removed, without affecting any of the materials present in the device stack.

For most postetch polymer removal applications, a dual, dry and wet clean strategy is employed. Typically, the dry plasma contains N₂/H₂ (forming gas), oxygen, and CF₄, and the wet clean is solvent based. It is desirable to minimize the wet clean portion for environmental and cost reasons. However, cases exist where either the postetch polymer formation is so severe or the sidewall polymer created during the etch is compositionally so complex that a strong wet clean and/or a dry clean with a large amount of fluorine-containing chemistries will be needed to remove the residues. The use of large quantities of fluorine-containing chemistries, such as CF₄, can result in unacceptable damage to titanium nitride (TiN) and dielectric layers that may be exposed to the plasma. Furthermore, there is increased potential for particle generation.¹ Previous research has indicated that the addition of H₂O vapor to the dry polymer removal process can provide a solution to difficult polymer removal problems.^2–5 This article extends those findings to a low-k, post-via-etch application.

Polymer Removal Following Via Etch

Postetch via sidewall polymer residues typically consist of C_xF_y with other metallic, organic, and/or silicon-based molecular clusters incorporated into the C_xF_y polymer matrix.⁶ Postetch metal line residues usually have a higher metal and metal oxide content. The organic additives derive from photoresist and generally have a C_xH_y molecular structure, which can be easily removed in ash processes. For the remaining polymer matrix, however, traditional oxidation plasma processes are not very effective, and fluorine must be added to the cleaning plasmas. In contrast to ashing processes that use oxidizing or reducing plasma chemistries for resist removal, polymer removal is carried out in the neutral plasma regime.^7,8

Figure 1: Active species concentration versus hydrogen-to-oxygen atomic ratio in typical downstream ashing plasma. Box indicates the area of interest.

Figure 1 shows the active species concentration versus the hydrogen-to-oxygen (H/O) atomic ratio in typical downstream ashing plasmas.³ Oxidizing reactions take place at the left side of the graph, where the O* concentration is higher than that of H*, while reducing reactions take place at the right side, where the H* concentration is higher than the O*. Neutral plasmas are defined in the boxed region, where OH* and a balanced amount of H* and O* are present in the plasma. H₂O vapor is a common source for O*, H*, and OH*, and the balance of these plasma species can be controlled by regulating the amount of H₂O vapor added to the plasma.⁹ The scanning electron microscope (SEM) images in Figure 2, which show metal lines following a postetch plasma process, indicate that sidewall polymer removal is most effective in the neutral regime with a medium H₂O vapor flow.

Experimental Conditions

The Axcelis Technologies facility in Rockville, MD, and Philips Semiconductor (Nijmegen, The Netherlands) have been conducting joint research into the mechanisms of postetch polymer removal using H₂O vapor–assisted plasma chemistries.³ The study described here focused on via-level polymer removal. The 0.18-µm-logic via process used in the study consisted of four elements: via lithography, via etch, an in situ strip, and the postetch via cleaning process. The via etch structures were defined by a film stack consisting of i-line photoresist; a bottom antireflective coating (BARC); a layer made of high-stress TEOS, flowable oxide (FOx) from Dow Corning (Midland, MI), and silox; and etch stops on a TiN ARC layer.

Figure 2: SEM images of metal lines following postetch polymer removal using various levels of H2O vapor in the plasma: (a) low H2O, (b) medium H2O, and (c) high H2O.

The via structures were etched in an RIE Model 4520XL etcher from Lam Research (Fremont, CA) using C₄F₈/O₂/N₂/Ar etch chemistry and were stripped in situ with an oxygen ashing step. Polymer removal was performed in an Axcelis FusionGemini ES microwave downstream asher using a plasma that consisted of forming gas and CF₄. The forming gas was a mixture of 3% H₂ and 97% N₂. The asher is a dual-chamber, radiantly heated, dry-strip tool that uses a proprietary remote microwave plasma source to produce activated, neutral species with minimal ion content. Typically, oxygen, forming gas, and application-specific minority gases such as CF₄, CHF₃, and H₂O vapor are used in the asher for photoresist and residue removal.

Figure 3: Schematic diagram of the water vapor delivery system.

During the study, H₂O vapor was introduced by a vapor delivery system from MKS Instruments (Andover, MA), which is shown schematically in Figure 3. It combines a vaporizer, a pressure-based mass-flow controller, controller electronics, and a power supply, and provides a precisely controlled flow of vapor that is low in metallic impurities.¹⁰

Various H₂O vapor–assisted plasma approaches were evaluated for the via clean application based on several criteria:

• Effectiveness of postetch polymer removal.

• Preservation of the TiN barrier.

• Preservation of the oxide cap layer.

• Preservation of the low-k material.

• Maintainability of low particle performance.

• Short process time per wafer (i.e., high throughput).

In-line SEM analysis was used to monitor the via sidewall polymer removal efficiency of different process approaches. In tests using an N₂/H₂/CF₄/H₂O plasma chemistry, it was determined that process temperature is the key parameter for successful polymer removal. Low wafer temperatures are required to render the polymer material water soluble. The investigations also showed that the inclusion of an intermediate step, in which the wafer is exposed to forming gas and H₂O vapor in the absence of plasma, improves polymer sidewall separation and solubility. Based on these findings, a three-step cleaning process was developed: 30-second exposure to an N₂/H₂/CF₄ plasma, 60-second exposure to an N₂/H₂/CF₄/H₂O vapor without plasma, and 60-second exposure to an N₂/H₂/CF₄/H₂O-vapor plasma. An intermediate vapor flow is used in step two.

Figure 4: Comparative SEM images of isolated and dense vias (a) after N2/H2/CF4/H2O-vapor processing, and (b) after N2/H2/CF4 processing. Left image is after etch, middle image is after dry plasma clean, and right image is after postclean rinse.

The SEM micrographs in Figure 4 compare the results of a standard N₂/H₂/CF₄ via clean process with those of the H₂O vapor–assisted process. Isolated and dense vias are shown after the etch (left), after the via clean (center), and after a subsequent DI-water rinse (right). After the etch, almost no polymer can be seen inside the via holes because it is stuck to the sidewalls. As Figure 4a clearly shows, however, after processing with the N₂/H₂/CF₄/H₂O-vapor recipe, polymer separated from the via sidewalls and was removed by the DI-water rinse. In contrast, as seen in Figure 4b, the standard N₂/H₂/CF₄ process, which is performed at high wafer temperatures, did not loosen the sidewall polymer. Some of the polymer eventually separated from the sidewalls, but because it was not water soluble, it was not removed by the rinse.

Figure 5: Comparative DSP via yield data for (a) a standard N2/H2/CF4 process, and (b) the H2O vapor– assisted process, both of which were followed by a DI-water rinse. Red dies indicate electrical resistivity failures.

The electrical performance of vias cleaned using the H₂O vapor–assisted process and the standard N₂/H₂/CF₄ process was compared using Philips Semiconductors' process evaluation module (PEM). Both processes were followed by a DI-water rinse. The PEM evaluated via resistivity in a digital signal-processor (DSP) module at the via 4 level. This module is a via configuration that simulates a DSP circuit. The results, shown in Figure 5, clearly indicate that wafers cleaned using the H₂O vapor–assisted process have a better yield performance than wafers cleaned using the standard process recipe.

Process Recipe Resistance at 60% Yield Below 6 Ω (%) Standard plasma + rinse 2.421 77.9 H2O vapor plasma + rinse 2.370 92.1 Rinse only 2.424 88.6

Table I: Cumulative probability data for via resistance and yield in a 1 million chain of DSP vias.

Table I lists the resistance and yield data from a representative wafer lot for the standard plasma process followed by a rinse, the H₂O vapor–assisted process followed by a rinse, and a rinse only. The best electrical performance was obtained with the H₂O vapor–assisted recipe, which achieved a yield of 92.1%, compared with 77.9% for the standard recipe. Yield data are plotted as a function of via chain length in Figure 6, which shows that the H₂O vapor–assisted process had the highest yield for all of the via chain lengths that were tested.

Figure 6: Yield data as a function of DSP via chain length for various cleaning processes.

In addition to its success in via-cleaning applications, the H₂O vapor–assisted plasma approach yields benefits in other IC manufacturing steps, as shown in the SEM micrographs in Figure 7. The figure compares the results from a standard CF₄-based plasma recipe with those from an H₂O vapor–assisted process for post-metal-etch, shallow-trench-isolation, and passivation-level applications.

Selectivity to Nitride and Oxide

During the postetch polymer removal process, the TiN etch stop and various oxide layers are exposed to the plasma. Therefore, tests were performed to assess whether adding H₂O vapor to a polymer removal recipe has any effect on TiN and oxide loss. Table II compares the thickness loss of the TiN layer and that of a thermal oxide layer following O₂/CF₄ plasma processes that included differing amounts of H₂O vapor. The plasma used was approximately 15% CF₄, which is capable of considerable nitride and oxide etching. The table shows that when H₂O vapor was added to the plasma, the TiN and oxide etch rates were reduced to below the 20-Å detection limit.⁴

% H2O Vapor Oxide Loss (Å) TiN Loss (Å) 0 133 1160 2 3 <20 5 <2 <20

Table II: Comparative oxide and TiN loss using various amounts of H2O vapor in a plasma composed of 85% O2 and 15% CF4.

Using SEM images of device structure cross sections, SiO₂ thickness was also determined. These results indicated that there was very good agreement between the actual measured thickness of the intermetal dielectric layer and the thickness calculated from electrical measurements. Normally, the use of forming gas (N₂H₂) improves selectivity to SiO₂, as does the addition of H₂O vapor to the cleaning recipe.⁷

Figure 7: SEM images comparing the effectiveness of a standard CF4 plasma process (at left) and an H2O vapor–assisted process (right) for three postprocess residue removal applications: (a) passivation level, (b) metal etch, and (c) shallow-trench isolation.

Conclusion

It is crucial to device yields to remove postetch polymer residues from interconnect structures, but it is also necessary during residue removal processes to maintain very low levels of TiN, tungsten, and oxide loss, as well as tight control over critical dimensions. In many cases, the addition of H₂O vapor to a wafer-cleaning process can enhance its polymer removal capability. The study reported in this article compared a CF₄/H₂O/forming gas plasma chemistry with the standard CF₄/N₂/H₂ plasma approach for via sidewall polymer removal. A low-temperature (<80°C) three-step recipe with an intermediate nonplasma H₂O vapor–assisted step was found to be capable of detaching polymer from the via sidewall and rendering it water soluble. Test data revealed that via yields were higher with the H₂O vapor–assisted process than with the standard recipe. Finally, it was shown that within the precision of existing measurement tools, the recipe does not affect the structures' TiN barrier or oxide layer adversely.

Acknowledgments

The authors would like to thank Bert Engelberts, Lukas Vermeulen, and Izaak de Haan of Philips Semiconductors in Nijmegen, The Netherlands, for their tool support.

References

1. A Rastegar, M Broekaart, and R Sonnemans, "The Effects of CF₄ and H₂O Flows on Particle Generation in Forming-Gas-Based Downstream Plasma Strip Processes," Philips Semiconductors internal report (Nijmegen, The Netherlands: Philips Semiconductors, 2002).

2. R Ruffin et al., "H₂O Vapor Assisted Plasma Chemistry for Photoresist and Polymer Removal over Low-k Materials," in Proceedings of the Electrochemical Society, vol. 2000–27 (Pennington, NJ: Electrochemical Society, 2000), 201–206.

3. C Waldfried et al., "New Plasma Chemistries for Polymer and Residue Removal," in Proceedings of the First International Conference on Semiconductor Technology, vol. 2 (Pennington, NJ: Electrochemical Society, 2001), 521–530.

4. C Waldfried et al., "H₂O Vapor Assisted Plasma Chemistry" (paper presented at the Sematech Wafer Cleaning and Surface Preparation Workshop, Austin, TX, May 2001).

5. D Higgins et al., "Strip, Etch, and RTP Benefit from Integrated Water-Vapor Delivery," Solid State Technology 44, no. 2 (2001): 89–92.

6. A Rastegar, "Via Etch Residue, Its Formation, Removal, and Impact on the Etch," Philips Semiconductors internal report (Nijmegen, The Netherlands: Philips Semiconductors, 2002).

7. M Fayolle et al., "Integrating of Cu/SiOC in Cu Dual Damascene Interconnect for 0.1-µm Technology," Microelectronic Engineering 64, no. 1 (2002): 35–42.

8. C Waldfried, Q Han, and J Kuo, "Reducing Plasma Chemistry for Photoresist and Residue Removal over Low-k Materials," in Proceedings of the Electrochemical Society, vol. 2000–27 (Pennington, NJ: Electrochemical Society, 2000), 207–212.

9. J Kikuchi et al., "Effects of H₂O on Atomic Hydrogen Generation in the Hydrogen Plasma," Japanese Journal of Applied Physics 32 (1993): 3120–3124.

10. B Cole, "An Integrated Water Vapor Delivery System for Improved Dry Strip and Residue Cleaning" (paper presented at Semicon West, San Francisco, July 9–12, 2000)

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Carlo Waldfried, PhD, is a senior scientist at Axcelis Technologies in Rockville, MD, where he is responsible for the development of new plasma chemistries and low-k processing. Before joining Axcelis, he developed advanced data-storage technologies. Waldfried has authored and presented many articles on surface science, magnetism, and semiconductor process technology. He holds several patents in the area of semiconductor processing. He received an MS in physics from the University of North Dakota in Grand Forks and a PhD in physics from the University of Nebraska in Lincoln. (Waldfried can be reached at 301/284-5215 or carlo.waldfried@axcelis.com.)

Roger Sonnemans is a senior applications engineer at Axcelis Technologies in Agrate Brianza, Italy, where he is responsible for application support, marketing support, and process development. Before joining Axcelis, he worked at Philips Research, where he was a process engineer in the dry-etch cluster area. He studied process technology at Mittelbare Technische School in Roermond, The Netherlands. (Sonnemans can be reached at +31 77 4661519 or roger.sonnemans@axcelis.com.)

Orlando Escorcia is a process engineer at Axcelis Technologies in Rockville, MD, where he is responsible for developing processes for low-k materials. Before joining the company, he worked for Commonwealth Scientific Corp., developing ion beam electron sources. Escorcia has coauthored many articles on semiconductor process technology. He received a BS in chemistry from the National University of Nicaragua in León. (Escorcia can be reached at 301/284-5088 or orlando. escorcia@axcelis.com.)

Ivan L. Berry is director of technology in Axcelis Technologies' cleaning and curing systems division. His focus includes advanced wafer cleaning; low-k dielectrics; and UV, plasma, and ion beam technology. Before joining the company, he worked on the development of ion projection lithography and was cofounder of the advanced lithography group consortium. He has worked in semiconductor processing for more than 25 years and pioneered the development of focused ion beam technology. Berry, a member of IEEE, ECS, AVS, and SPIE, has authored and presented many articles on wafer cleaning, semiconductor processing, and ion beam technologies. He received a BSEE from Drexel University in Philadelphia and an MS in applied physics from Johns Hopkins University in Baltimore. (Berry can be reached at 301/284-5557 or ivan.berry@axcelis.com.)

Abbas Rastegar, PhD, is a senior process engineer at Philips Semiconductors in Nijmegen, The Netherlands, where he is responsible for the development and characterization of oxide (low-k) etch and postetch clean processes. He has published many articles on surface and interface physics and nanoscience. Rastegar is a member of the extreme UV lithography group of International Sematech, working on advanced cleaning methods for EUV mask blanks. He received BS and MS degrees in solid-state physics from the University of Mashhad, Iran, and a PhD in physics from the University of Ljubljana, Slovenia. (Rastegar can be reached at +31 24 3536395 or abbas.rastegar@sematech.org.)

Marcel Broekaart is a senior process development engineer at Philips Semiconductors in Crolles, France, where he is responsible for new back-end dry etch applications for CMOS 90- and 65-nm technologies. After working on quantum point contacts at Philips Research Laboratories, he worked in the lithography area for seven years. Broekaart joined the Philips/ST Crolles project in 1996, working on back-end etching and stripping. In 1999, he transferred to the Philips MOS4 facility in Nijmegen. He rejoined the Crolles 2 project in 2001. He received an MS in physics from the University of Eindhoven, The Netherlands. (Broekaart can be reached at +33 4 76925155 or marcel.broekaart@philips.com.)