'Round The Circuit

Lab: films to meet map goals

Thin barrier films will satisfy the tight requirements defined in the semiconductor industry's technological roadmap, Infineon Technologies reports. The German chipmaker says its researchers recently shrunk film thicknesses to nanotechnology dimensions in order to demonstrate the ability of thin films to meet the metallization needs of next-generation devices. Specifically, the results indicate that the films will meet the electrical and functional targets all the way to the end of the International Technology Roadmap for Semiconductors in 2016, Infineon says.

In testing the scaling limits of Ta/TaN barrier technology, a team at Infineon's Munich Research Labs assessed the integration of metallic films required to keep copper metal lines from diffusing into the transistors underneath device wiring. Working at film thicknesses below 2 nm, the researchers also stretched the capability of current deposition techniques, Infineon notes.

SEMI releases 13 standards

Best practices for welding fluid-distribution systems in fabs and guidelines for calculating factory efficiency are among a set of 13 new standards published by SEMI. The technical standards cover areas of both semiconductor and flat-panel display (FPD) manufacturing. The new benchmarks are part of the July 2003 publication cycle. SEMI publishes standards three times per year and has released more than 620 standards over the past 30 years.

The new releases "will provide further cost savings and economies of scale for the semiconductor and FPD manufacturing industries," says Bruce Gehman, SEMI's vice president of standards and CTO.

Participants from equipment suppliers, device houses, and other companies developed the 13 standards. The benchmarks also cover a guideline for gas compatibility with silicon used in gas distribution components, a specification for round 150-mm polished monocrystalline wafers, and a provisional specification for equipment self-description. All are available in CD-ROM format. They also can be downloaded from SEMI's Web site at www.semi.org.

Maskless tool called success

A new maskless lithography tool has created patterns at geometries as small as 50 nm, the tool's manufacturer claims. Mapper Lithography of Delft, The Netherlands, says the first tests of its multibeam, maskless technology show that the technique is suitable for making ICs at the 45-nm technology node. The company unveiled the results of the tests in a technical paper presented at the 3BEAMS conference in Tampa, FL, in late May.

The company takes its name from the system it developed, which stands for multiaperture pixel-by-pixel enhancement of resolution. The system's microlens array contains at least 13,000 light sources. Launched in 2002, the start-up plans to introduce a maskless tool by the end of 2005 or the beginning of 2006.

Motorola gets 'flash' tool

A lithography start-up with a new type of technology has shipped its first working tool to Motorola Labs. Molecular Imprints of Austin, TX, makes the system, called the Imprio 100, which Motorola will use for advanced research in areas such as novel devices, compound semiconductors, and molecular electronics.

Motorola and Molecular Imprints have worked together for two years in order to develop a working tool. The step-and-flash imprint system can create images at the sub-100-nm level, the supplier says. The bilayer technique uses a low-viscosity liquid etch barrier deposited on an underlying transfer layer. A rigid and transparent template permits UV curing of the etch barrier and the use of standard layer-to-layer alignment techniques.

The step-and-repeat process operates at approximately one-tenth of the cost of standard projection-based lithography, the company says. The system works at room temperature and in a low-pressure environment. The first-generation tool now at Motorola's research arm handles wafers up to 200 mm. A next-generation system due in 2004 should offer throughputs operating at production volumes, Molecular Imprints says.

Professors Grant Wilson and S.V. Sreenivasan of the University of Texas in Austin developed the step-and-flash imprint technology. Molecular Imprints has an exclusive license to develop and use the technology. (For more on nanoimprint litho, see the lead story in Industry News in MICRO's June 2003 issue.)

IEST publishes outgassing RP

IEST has released a new recommended practice (RP) covering outgassed organic compounds. Method for Characterizing Outgassed Organic Compounds from Cleanroom Materials and Components (IEST-RP-CC031.1) offers users a technique for the preliminary screening of the compounds.

The RP describes a test method for semiqualitative characterization of organic compounds released from materials or components exposed to air in cleanrooms and other controlled environments. The practice detects outgassed compounds using dynamic headspace gas chromatography– mass spectrometry. IEST Working Group WG-CC031 developed the document under the chairmanship of Victor K. F. Chia. IEST-RP-CC031.1 is available at www.iest.org or at publicationsales@iest.org. The institute's number is 847/255-1561.