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Developing and implementing an advanced CMP run-to-run controller

Anthony J. Toprac, Yield Dynamics; and Hector Luna, Brad Withers, Mark Bedrin, and Stephen Toy, NEC Electronics America

Chemical-mechanical polishing (CMP), an essential operation in microelectronics manufacturing, is the process of removing material from a topographically varied silicon wafer surface so that the surface is effectively planarized. The density, height, and geometric form of the topographic variation on the wafer surface are specific to the manufacturer's product and manufacturing process.

Typical CMP tools polish by forcing the variegated surface of a wafer against an abrasive polishing pad, which is mounted on a rotating platen that is typically several times larger than the wafer. In addition to the rotation of the platen, the wafer itself rotates about its center point.

All CMP tools distribute a liquid slurry across the polishing pad. Slurry provides both mechanical abrasion and chemical reactions to remove material from the wafer surface.

Between wafer polishes, the pad must be conditioned. Conditioning typically involves applying an abrasive or cutting element, such as a diamond wheel, to the pad surface to restore its roughness.

As with any manufacturing operation, the CMP process falls victim to many known and unknown disturbances that affect its controlled operation. Variations among incoming wafers, process temperatures, polishing by-products on the pad, mechanical tolerances caused by wear, and polishing consumables (slurry and pads) all contribute to uncontrolled drift in polishing process results. Virtually all CMP processes, therefore, update polishing tool recipes either automatically or manually to compensate for such disturbances.

The most effective means of compensating for disturbances is automated run-to-run (R2R) control, batch supervisory control techniques that have been used for many years in the chemical process industry. Run-to-run controllers use preprocess metrology data as feedforward information and postprocess metrology data as feedback information to automatically update operating process recipes. A schematic diagram of the enTune CMP R2R controller from Yield Dynamics (Santa Clara, CA) is shown in Figure 1.

Figure 1: Run-to-run control scheme applied to the CMP process.

R2R controllers are an interwoven combination of logic rules, configuration methods, database schema, and mathematics. At the heart of any R2R control system is the control model, a mathematical expression that maps the control "knobs," or manipulated variables, to measured process results. Since control model formulation is unique to each application, it often represents the most time-consuming development task in implementing R2R control.

Developing a Control Model

A good control model has several key characteristics. Accuracy requirements for control models are relaxed by using feedback data to continuously recalibrate within a relatively narrow region of operation. Robustness and speed of execution, however, are paramount concerns for control models; failures or delays in solving model equations can cause costly disruptions in manufacturing processes.

An emphasis on robustness and execution speed over accuracy compels control engineers to follow the philosophy that simpler is better when developing their models. Consequently, control models always represent a significant reduction of true process complexity. Simplified models arise either from a priori mathematical decisions (e.g., by selecting a linear model) or from a reduction of complex models (typically represented by physical or chemical descriptions of the process).

Such complex models are sometimes available in the form of commercial process simulators. However, off-line process simulators have very different requirements than control models. They require a high degree of accuracy over a wide range of operating conditions as opposed to robustness and execution speed, which are much less critical in off-line environments. As a result, the direct use of simulators as control models is, in general, not practical.

Although not directly usable in control applications, simulators nonetheless form an excellent starting point for developing control models. During development, simulators take the place of physical process systems, facilitating extensive experimentation without the expense associated with performing actual experimental runs. In addition, a simulator's mathematical process description can serve as the basis of a control model. The reduction of a complex model to an appropriate control model is an engineering art in which empirical approximations, linearization, and the elimination of spatial dimensions are all part of the control engineer's toolbox.

Modeling the CMP Process

This article describes an advanced CMP R2R control model developed by reduction of a commercially available, complex, nonlinear process simulator. The Mesa simulator from Scott Runnels Consulting (Los Alamos, NM) accurately portrays the CMP process at microfeature scale by approximating the polishing pad as a linearly elastic system.1–3

Figure 2: Schematic of the Mesa model of the polishing pad as a linear elastic system.

The polishing pad model is illustrated in Figure 2. The wafer rests above the polishing pad with its patterned side forced face down into the pad. The reaction force of the pad on the wafer is modeled by two linear spring forces, a normal force with spring constant k1 and a bending moment with spring constant k2. These spring constants are characteristics of the polishing pad material and can be identified from operational or experimental data. The sum of the resulting forces is used to define the shear forces and, consequently, the removal rates on microscale wafer features. Based on that calculated removal rate, the simulation tracks the evolution of microfeatures over time as they are polished to planarity.

Figure 3: Comparison between Mesa model predictions (red line) and CMP tool polishing results (profilometer scan, black line) for copper polishing operation.

Numerous studies have validated the Mesa simulation model against operating CMP tool data.1–3 The results of one such study are shown in Figure 3, which plots Mesa predictions, indicated by the red lines, against copper polishing profilometer scan data, indicated by the black lines. The evolution of the polished surface from short polishing times (upper plots) to long polishing times (lower plots) is indicated by plotting feature heights on the y-axis against lateral distance across the die on the x-axis. This comparison verifies the overall validity of the simulator, showing the transition from high nonplanarity to planarity to dishing as polishing proceeds from short polishing times to overpolishing times.

This detailed microscale simulator description of planarization was used to develop a new, advanced model for use in CMP R2R control applications. Typical CMP R2R control assumes that the amount of film removal on high features can be calculated as polishing time multiplied by an estimated removal rate. The estimate of removal rate is updated as process results become available from postpolish metrology. Often an empirically determined, device-dependent scaling factor is applied to the polishing rate to account for differing high-feature densities among different products. Prepolish measurements of film thicknesses are used to determine how much film must be removed, accounting for variations among incoming wafers.

While providing functional R2R control in CMP applications, such simple linear models do not compensate for some significant sources of variation in the polishing process. In particular, although such models provide a rudimentary estimate of removal rate, planarization rate (i.e., high-feature versus low-area removal rate) is the critical variable to track and control in the CMP process. R2R controllers based on a simple linear model often compensate for variations in prepolish film thickness but ignore the critical variable of the prepolish height of high features above low areas. In addition, while simple CMP controllers account for differing pattern densities among products using empirically determined scaling factors, they offer no explicit model that uses known pattern-density values from photolithography mask characteristics. Simple CMP process models also do not predict planarization rate as a function of the key recipe variables of downforce and platen speed.

However, the biggest flaw in typical linear models is their assumption that removal rate is not a function of polishing time. In fact, the removal rate declines significantly as polishing times increase.4 At short polishing times, the polishing rate for high features is maximized; as the wafer surface approaches planarity, the polishing rate declines to that of unpatterned planar wafers.

Modeling Planarization Rate: A New Approach to CMP Control Models

The CMP planarization control model discussed in this article predicts the film thickness of high features as a nonlinear function of key incoming wafer characteristics and polishing recipe variables:

ym = f (t, ho, S, M, Fdn, k1)

where ym = the film thickness of high features, t = polishing time, ho = prepolish feature height, S = polishing speed, M = mask % chrome, Fdn = downforce, and k1 = normal force pad spring constant.

The dependency of planarization rate on the simulator model's bending-moment spring constant k2 is handled heuristically. The model state, updated on a run-to-run basis from available metrology data, is the coefficient C in Preston's equation:

where S is the pad-to-wafer relative velocity and Fnet is the reaction force on high features.5

Achieving the postpolish target for high-feature thickness is constrained by the need to achieve minimum planarity:

h = f (t, ho, S, M, Fdn, k1) ≤ max allowed height

where h is the average height of high features above low-patterned areas. To minimize dishing, model predictions of the removal rate in low-feature areas place an additional constraint on maximum low-feature thickness loss.

Figure 4: Comparison between CMP planarization model polishing rate predictions (lines) and Mesa simulation results (points) for three different feature heights.

Figure 4 compares the CMP planarization control model data with the more detailed predictions of the simulator, where the new control model data are represented by a solid line and simulator results are indicated as data points. The three conditions labeled 13K, 15K, and 18K represent three different prepolish microscale feature height values. The impact of feature height variation on the planarization rate is shown to be quite significant. In addition, there is a clear transition in the functional dependency of the planarization rate on polishing time, an effect that becomes increasingly important for higher prepolish features.

Use of the New Model in CMP R2R Control

The new CMP control model form was verified by a set of experiments performed at NEC Electronics America's fab in Roseville, CA. First, oxide thickness was measured on both high- and low-feature areas on 50 product wafers. Then each wafer in sequence was polished for 10 seconds longer than the previous wafer, with the final wafer receiving 20 seconds more than the nominal polish process time. After that polishing step, the wafers' oxide thickness was remeasured, and then the wafers were polished again so that the sum of the first and second polishes equaled the nominal polishing time. Consequently, when the wafers were polished the second time, they had very different initial feature heights and thicknesses.

Figure 5: Comparison between model prediction data (line) and actual measurement data (points) for high-feature thickness after the first polish. Model calibration was based on the historical planar removal rate and was not regressed to fit the experimental data.

Figure 5 compares model predictions to actual measurements of high-feature thicknesses after the first polishing step.5 The model's calibration of Preston's coefficient was based on the typical process value for the planar-wafer removal rate and not explicitly regressed to provide an optimal fit to the data. Nonetheless, the model accurately predicted actual measured thicknesses after the product's first polish.

The rework procedure, the repolishing of the partially polished wafers, offered an opportunity to compare the effectiveness of the new model with that of traditional CMP R2R control methods. Postrework polish thicknesses from the new control model and a traditional control method were estimated by fitting the measured postrework thicknesses to a quadratic polynomial of actual rework polishing times. Thicknesses were predicted for each wafer using a linear model that intersected the wafer's measured thickness value and used a slope determined by the derivative of the fitted polynomial evaluated at each wafer's experimental polishing time. Applying the polishing time calculated using either method to this linear equation provided an estimate of the resulting postpolish thickness for each wafer.

The traditional CMP R2R control method calculates film removal rate by dividing thickness loss by polishing time, filtering that state estimate by means of an exponentially weighted moving average. The amount of film that must be removed from each wafer divided by the filtered state estimate provides a value for the required polishing time.

In contrast to the traditional control method, the new model uses measured film thickness removal to recalculate Preston's coefficient as the control model state. Since the predictions from the new model incorporate measurements of both initial wafer feature height and thickness, the new model should be superior to the traditional one, which only accounts for prepolish thickness variations.

Data Source Mean Standard Deviation Cpk
Actual measurements 7746 0.0440
New control method 7775 0.0428
Traditional control method 7735 0.0471

Table I: Summary of performance statistics for actual, new, and traditional control methods. The new method represents a 6% improvement in Cpk and matches the actual rework results based on perfect knowledge of required polishing time.

In the experiments presented here, performance statistics were calculated for the actual rework process, the new CMP model controller, and the traditional control method on a wafer-to-wafer basis. Each controller's state estimate was arbitrarily placed 10% higher than the optimal value for the first wafer, requiring that both controllers adjust for initial model error. The simulations included a one-wafer delay between polish and postpolish measurement. The results of these simulations are summarized in Table I, which shows that the new method was in fact superior to the traditional one, with a 10% lower process standard deviation and a 6% higher estimated process capability (Cpk) value.

Figure 6: Comparison between model prediction data (lines) and actual measurement data (points) for three polishing times and two different feature densities. The two feature densities varied by about 20%, which the new model tracks based on the input of mask layout densities.

While this experiment validated the incorporation of feature height as an important input variable in modeling planarization, the verification of the model's dependence on feature density required a second experiment. That experiment involved polishing different feature densities and measuring the amount of material that was removed. Figure 6 compares the new model's prediction of postpolish thickness with the measured value for two different feature densities over three polishing times. The only model input that differed between the feature densities was the ratio of high-feature to total polish area from the photolithography mask layout. That difference was approximately 20%. Using only a priori knowledge of mask layout feature density, the new model provided accurate estimates of material removal as a function of polishing time.


An innovative model for R2R control of CMP processes was developed based on the Mesa microscale polish simulator. The model accurately predicts planarization rate—that is, the polishing of high wafer-surface features relative to low features as a function of critical recipe variables (e.g., polishing time, downforce, and platen speed) and important incoming product characteristics (e.g., prepolish feature height and pattern density). In addition, the model captures the nonlinear dependence of planarization rate on polishing time. The model represents a significant improvement over typical CMP control models, which employ a rudimentary description of polishing rate as constant over polishing time and do not model downforce, platen speed, or critical product characteristics such as feature height and density.

The new R2R controller provides an accurate, device-dependent prediction of planarization rate on new products before the first polish. It tracks the state of the CMP tool across recipes with differing downforces and platen speeds, enabling the automated system to update the controller consistently. Moreover, by correctly describing the nonlinear
dependence of planarization rate on polishing time, the system can automate the calculation of the polishing time required to rework underpolished wafers.

Beyond improving process control, the control model allows engineers to eliminate costly and time-consuming short-polish characterization experiments, which have traditionally been required to determine both nominal polishing times and rework curves for new devices and layers. Such experiments can take four to six man-hours and reduce the availability of production equipment. In order to manufacture 20 different devices containing five dielectric levels, a fab using a traditional CMP controller would have to perform 100 short-polish experiments. Using the new model, it would only have to perform one. As many fabs manufacture increasing numbers of devices and polish more and more back-end layers, this benefit should find expanding recognition in years to come.


The authors would like to thank Scott Runnels from Scott Runnels Consulting (Los Alamos, NM) for providing the Mesa CMP simulator and offering key technical consulting in the development of the new CMP control model. They would also like to thank Thomas Laursen from Novellus (San Jose) for providing the CMP data shown in Figure 3.


1. SR Runnels, I Kim, and F Miceli, "Implementing Large Area 3D Erosion Simulation," in Proceedings of the 1999 Chemical-Mechanical Planarization for Multilevel Interconnect Conference (Tampa, FL: IMIC, 1999), 128–135.

2. T Laursen et al., "Modeling of Feature-Scale Planarization in Cu CMP Using Mesa," in Proceedings of the 1999 Advanced Metallization Conference (Warrendale, PA: Materials Research Society, 2000), 677–681.

3. T Laursen, SR Runnels, and AJ Toprac, "Application of Mesa Modeling for Chemical Mechanical Polishing," in Proceedings of the 2000 Advanced Metallization Conference (Warrendale, PA: Materials Research Society 2000), 205–209.

4. AJ Toprac, "Model-Based Control of Chemical Mechanical Polishing," in Proceedings of SPIE, vol. 3213, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing III (Bellingham, WA: SPIE, 1997), 101–107.

5. FW Preston, "The Theory and Design of Plate Glass Polishing Machine," Journal of Glass Technology 11, no. 44 (1927): 214–256.

Anthony J. Toprac, PhD, is vice president of APC solutions and director of the APC development center of Yield Dynamics (Austin, TX). A registered professional engineer, he received a PhD in chemical engineering from the University of Texas in Austin. (Toprac can be reached at 512/257-9500 or

Hector Luna is a CMP process engineer at NEC Electronics America (Roseville, CA), which he joined in 2000. He received a BS in chemical engineering from the University of California, Davis. (Luna can be reached at 916/786-3900, ext. 5915 or

Brad Withers is a staff process engineer at NEC Electronics America, where he has been since 2001. He holds two patents and has authored several papers on CMP technology. He received a BS in materials science and engineering from California Polytechnic State University in San Luis Obispo. (Withers can be reached at 916/786-3900, ext. 5917 or

Mark Bedrin is a senior equipment engineer and system administrator for advanced process control systems and equipment communications at NEC Electronics America. He has been with the company since 1995. He received as BS in mechanical engineering from California State University in Sacramento. (Bedrin can be reached at 916/786-3900, ext. 4743 or

Stephen Toy is a CIM automation and wafer test equipment engineering manager at NEC Electronics America, where he has been since 1989. He holds four patents in the field of semiconductor equipment design. He received a BS in electrical engineering from California State University in Chico. (Toy can be reached at 916/786-3900, ext. 4823 or

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