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LITHOGRAPHY:

Challenges Abound on Road to 45 nm and Beyond

Welcome to the first installment of "The Hot Button." In each issue, this feature will present discussions by industry experts about the critical challenges facing one of four key focus areas within advanced chip manufacturing: lithography, metrology, interconnect, and fab automation/integration.

This issue's Hot Button deals with lithography, the sine qua non of chipmaking process modules. The feature presents selected comments made at a recent panel session sponsored by Cymer, held in conjunction with the excimer light source company's lithography symposium at Semicon Japan in early December. The panel, moderated by Tony Yen of Cymer, included representatives from the three main exposure tool companies, a leading mask house, and litho strategists from Intel, Sony, AMD, NEC, and TSMC.

The panelists were asked the following questions. First, what technology do you think will be needed for the 45- and 32-nm nodes? Will that technology be ready in time? What are the development challenges? What do you think the backup technology will be at each node? Secondly, is the industry currently investigating too many lithographic technology options? If so, which ones should be selected for focus and work? Lastly, what does design for manufacturing (DFM) mean to you? What specific approaches do you think will be most successful in this area?

Here are edited portions of the participants' answers to these questions, offering a glimpse into how some of lithography's leading lights see the world of nanometer-scale patterning.

KUNIHIRO KASAMA (senior manager, advanced technology development division, NEC Electronics): Device manufacturers tend to be very conservative. For my side, NA (numerical aperture) if it's below 0.35, k1 factor, if it's below 0.35, CD will be very limited. Looking at MEF (mask error factor), it is going to be very large, and CD precision is going to suffer. Therefore, as much as possible, we would like to maximize k1 factor at the 0.35-NA level. The approach or direction is more or less decided at 65 nm... ArF (argon fluoride) immersion is the technology that we would like to use. Looking out toward 2009, 2010, 45-nm half-pitch, it would be F2 (fluorine) immersion or EUV (extreme ultraviolet). They are the only technologies that seem to be feasible... F2 immersion is below 0.35 NA, so it is also very difficult. We will have to use strong RET (resolution enhancement technology) and focus margins. Polarization property was also mentioned and must be taken into account. At 45-nm half-pitch, even with F2 immersion, I think it's going to be very difficult.

Keeping that in mind, I would like to come back to the questions posed. First, at 45- and 32-nm nodes, what is the lithography technology needed or used? At the 45- or 65-nm half-pitch, it's ArF immersion and F2 dry. As for 32 nm, it's EUV.... ArF immersion, if it is successful, then after that we would like to come to the F2 immersion possibility. The fluid issue—absorption—remains, so we have to overcome this issue. First we would like to complete ArF immersion and then consider the possibility of F2 immersion. As for whether we can develop this in time, with ArF immersion... there's no visible showstopper, but according to...ASML, we do not know what may happen. So the preliminary examination stage is where we are at.

HIROICHI KAWAHIRA (general manager, lithography, technology department, process development division, Sony Corp.): As for the last question, DFM, layout CAD (computer-aided design) optimization [is needed]. Concerning that, how fast the cycle can be operated within the design will be the key. The layout will be determined first, and mask optimization will be conducted. It will be structural optimization—for example, alternating PSM (phase-shift mask) structure—how that can be optimized will be the issue here. Also, the aberration of the tools and process, how those can be optimized as well.

NAOYA HAYASHI (general manager, electronic device laboratory, Dai Nippon Printing): Will mask technology be ready in time? [For] 193-nm and F2 RET masks in terms of material fabrication, we already have the RET in place, and in terms of pellicles, you might say it's part of the mask. Mask handling, including pellicles for F2 and EUV, remain as challenges. Having said that though, of course there are development items that we need to continue to work on for the masks, which are CD control and defect dispositioning, or defect transfer.... How to judge the transferability of mask defects is a major challenge.

If the writing and inspection of masks can be standardized, we can reduce the cost. –Naoya Hayashi
PHOTOS COURTESY OF CYMER

Design for manufacturing: for the maskmaker, what does this mean? Well, you all point out often that the mask cost is exploding and we need to try to restrict that, and DFM could be one way to do that. OPC (optical proximity correction) has become very complex, and if you ideally design this, then the data volume, which has been exploding twentyfold in the past several years, could be limited. [As for] the production tool and the inspection tool, productivity is decreasing because of the data size, and the mask cost is rising as a result.

So what can we do about this? One thing is RET, [but it] needs optimization. You have to think about the benefit and the cost balance, and I think you can find the best solution. If the writing and inspection of masks can be standardized, we can reduce the cost; so from design data, the format of the data that you send to the maskmaker, if that can be standardized, it would be beneficial.

HARRY LEVINSON (manager of lithography development, Advanced Micro Devices): At least for logic, we could, in principle, achieve the 32-nm node with F2 immersion. The question is, do we want to develop a technology that will cover only half a node? It could cover it for logic but it doesn't cover it for memories. I think the answer is most likely no, if there is another choice, and I think that really is the question for F2 immersion: will there be an alternative to allow us to continue scaling, and also assuming that simply making things smaller is not really what you need to do. It's to provide better value for customers.

I think [what] designing for manufacturability means...is that the design part is used to achieve a low manufacturing cost. And some part of that design can also be integration.

Looser tolerances are things that make manufacturing easier.
–Harry Levinson

For example, self-aligned contacts would be something that would allow us to have easier manufacturing. Looser tolerances are things that make manufacturing easier. That is to say that if we can have functioning integrated circuits with looser overlay, or we may not need quite so tight focus control or quite so tight illumination uniformity and still get good yield, then we have achieved manufacturability through design.

Just as an example of what you can see, if you look at the ITRS, the
overlay requirement for the 45-nm node is 18 nm. Now, if we could relax that by only two nanometers, again through something like self-aligned contacts, the overlay budget is improved by 10%. That could be very, very helpful for manufacturing.

JANICE GOLDA (assistant director, lithography capital equipment development, Intel): When we think of DFM, we think of layout, but there's also high-volume manufacturing for us, which means starting several thousand wafers a week in multiple fabs around the world. So what are some of the big components we worry about? One is focused on the litho cost of ownership.... The tools need to be affordable, and being in Japan, this means how many wafers per hour do we get out of the tool per yen we pay for the tool.

Going forward to a very complex phase-shift mask, the things requiring multiple exposures, that cuts tool throughput very quickly as you go to a double exposure. This whole throughput is less than half of what it is for a single exposure, so we can't afford a lot of double exposure and complex mask steps.

The unnamed components of cost of ownership are really the yield and defect levels. –Janice Golda

The second [factor] is availability, and can our tools run at 95% uptime in high volume if the process is very marginal? The process needs to have some margin so we can run it at high availability and high utilization.

The unnamed components of cost of ownership are really the yield and defect levels. As we get to low-k1, these issues can be harder to debug as we attack the critical issues surrounding immersion. Getting the defect issues managed and under control will be a focus area to achieving the cost of technology....

The other main challenges that have been mentioned here are the layout constraints. We can apply some constraints to layout to make it more litho-friendly, and we've been doing that. But at some point, as you apply too many constraints, first of all it may impact your density, your cell size, as has been mentioned. Secondly, it may impact the cycle time for design as people need to work around more and more of these constraints.

And finally to wrap up, what we see is the wavelength transition, so in our case the next transition we see is 193 to EUV. It really occurs when we see the cost and complexity of the new technology being preferable to that of the existing technology, so as extending ArF gets more and more expensive, as EUV source power comes up, the cost, the affordability of the technology lines will overlap and we expect to see migration.


In MICRO's March issue, "The Hot Button" will focus on metrology.

 


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