INDUSTRY NEWS

ITRS UPDATE

Revised roadmap shows hard work ahead for yield drivers

No surprises lurk in the yield enhancement chapter of the new International Technology Roadmap for Semiconductors (ITRS). The latest revision of the semiconductor industry's guiding document shows that the same tough battle to detect and eliminate defects has become, well, even tougher.

ILLUSTRATION BY KELLY JOHNSON

"The science of yield enhancement is becoming increasingly complex due to ever-shrinking yield-detracting defects, nonvisual defects, high-aspect-ratio defects, and issues concerning design for manufacture, diagnosis, and test," notes Fred Lakhani, chairman of the international technology working group (ITWG), or twig, responsible for the selfsame chapter. Most of the yield enhancement updates "are incremental in nature," he emphasizes.

The chapter's authors define yield enhancement as "the process of improving the baseline yield for a given technology node from R&D yield to mature yield." The definition encompasses only wafer-sort yield. Within that definition, they note, several difficult challenges confront semiconductor manufacturers through 2010 at the 45-nm technology node and beyond.

In particular, three major tests loom for chipmakers and their suppliers. One, the industry needs to continuously improve tool cleanliness. Two, a pointed effort is required to understand and eliminate factors that detract from the widespread use of "systematic mechanisms limited" yield. Three, the industry needs to better understand and control the impact of line-edge roughness on yield in order to reach acceptable outputs.

Published in mid-December, the 2003 ITRS is the first full update since the 2001 edition. Extended to 2018, the completely revised document features both modified tables and text. The definition from the 2001–2002 version for the DRAM technology node remains unchanged, the authors note: It will stay at half-pitch for metal 1. A new status color has been added to the 2003 edition's technology requirements tables to identify where stopgap measures are available; patterned cells with red diamonds inside signify that "interim solutions are known." The revision also introduces other topics and advances. Immersion lithography debuts, as do so-called nonclassical CMOS devices and post-CMOS products such as nanoscale devices with variable logic states.

One of the major changes to the latest roadmap is the return to a three-year technology node cycle, stretching out the timeline between 130- and 90-nm an additional year. This decision will have an impact on wafer-sort yield recommendations, which remain pretty much the same despite the prolonged business slump, says Lakhani, project manager/SMTS, manufacturing methods and productivity, for International Sematech in Austin, TX. This timing "has helped relieve the yield ramp requirements by providing an additional year to ramp up to the target yield for the 90-nm technology node." However, he adds that recent data "from an internal Sematech survey suggest that the mature yields for leading-edge technology nodes are at a lower level than previous nodes."

The yield enhancement chapter is divided into four sections: yield model and defect budget, defect detection and characterization, yield learning, and wafer environment contamination control. The chapter introduction emphasizes the connection between a chipmaker's bottom line and rapid yield ramps, specifically with the advent of 300-mm processing. Of course, success assumes yield competence in all four groups, and these capabilities cut across all the process technologies, facility infrastructure, IC design, and process integration areas.

The cross-disciplinary nature of yield enhancement is reflected in several of the other chapters. In the roadmap work done for environment, safety, and health (ESH), participants evaluated the areas where ESH and yield enhancement intersected, explains Jim Jewett, the twig's chairman. "While we were unable to complete a set of mutual technology requirements for the 2003 ITRS, we did identify several for additional work in 2004–2005. These areas look at the potential impact on yield that might occur when driving toward some ESH goals.

"For example, resource conservation includes objectives on water conservation. In efforts to reduce the use of water, there are potential impacts on our ability to sustain clean levels and maintain yield. Another area relates to purity when considering recycle systems [because] chemical purity is a key issue in regard to yield. Driving both water and chemical recycling as part of the pollution prevention and resource conservation objectives of ESH may have a detrimental effect on material purity."

A third concern relates to the use of process material, says Jewett, a materials principal engineer and manager of Intel's strategic environmental programs. "Conservation of raw materials by improving utilization may be in conflict with yield efficiencies. In each of these areas, our intent is to evaluate the synergy and conflict potential and develop mutual ITRS goals based upon the results."

Not surprisingly, the thorny subject of process materials turns up in several of the chapters. The front-end processes (FEP) section—which takes in thermal/thin films, surface preparation, starting materials, and the like for MOSFETs, FeRAMs and other devices—declares: "We have entered the era of material-limited device scaling!"

Walter Class of Axcelis, chairman of the FEP twig, emphasizes that "the statement was not meant to send a doomsday message." The authors wished to stress that in the near term, "scaling will not be limited by advancements in photolithographic processes and photoresist materials, but by the introduction of new FEP materials and processes identified in the roadmap text. These include the introduction of high-k gate dielectric materials, dual-metal gates, and strained-silicon channel materials."

Everyone knows this; the 2001 edition also mentioned the problem, Class points out. "There is no denying that the introduction of these materials poses challenges that have not heretofore been encountered and, in reflection of that reality, the pace of roadmap scaling, which had been on a two-year cycle, is now forecast to retrench to a three-year cycle as it had been in the early 1990s."

As for silicon-on-insulator wafers, "it is also too early to tell how far SOI will have penetrated the market by the 2011 time frame," Class says. "The current ITRS suggests that devices made on SOI wafers will be required for leading-edge device manufacture, but it is not clear what fraction of the overall market will require SOI. I would also like to note that all roadmaps suffer from a common blind spot. We can identify the limitations of a current incumbent technology and, based on this, predict the need for enhanced technologies."

A classic example of this flaw was the predicted demise of optical lithography at the 1-µm technology node, Class points out. For this reason, it's hard to see bulk silicon wafers being replaced by 2011, whereas strained silicon will find commercial use in the very near future, he says, "unless some other means are found to create in situ strains in the device channels."

Acknowledging the complexity of chip design, the FEP section notes that devices with shallower scaling will require "completely benign" cleaning. "Process flows are becoming more complicated as chip designs include different transistor designs on the same chip," Class explains. "As a consequence, the number of cleaning steps is rapidly increasing. In addition, the active layers are getting thinner as scaled devices have more-shallow junctions, thinner gate dielectric layers, and the like. This suggests that cleaning steps must be developed that clean the surface of metal and particle contamination without removing any of the underlying substrate material."

Addressing the same issue, FSI's Jeff Butterbaugh, cochairman of the surface preparation "sub-twig," says the convergence of fragile gate structures and the need to minimize material loss preclude the use of megasonics for cleaning. This situation "is driving a red brick after the 65-nm node and also driving a lot of current surface preparation research and development." It's also driving "mask-level-specific cleaning processes...tailored specifically to the state of the wafer surface at that point in the process."

MICRO's roundup of the 2003 ITRS includes the following additional highlights:

• The surface preparation sub-twig, part of the interconnect twig, has begun working side by side with the wafer environmental contamination control group within yield enhancement to harmonize specifications on DI water, process gases, and cleanroom air with surface contamination requirements, says Butterbaugh. One area of high activity: a spec for dissolved oxygen and dissolved nitrogen levels in DI water.

• The tension between the need for fast cycle times and proper asset utilization has to be resolved, insists Jeffrey Pettinato of Intel, chairman of the factory integration twig. "At certain times, a fab will hold equipment until a 'superfast hot lot' comes, but you pay a penalty on [tool] utilization." The conflict between business and production can be addressed with faster cycle times, improved planning and scheduling systems, use of direct-transport automated material handling systems, and fabwide systems that better comprehend flow.

• On the advanced process control front, Pettinato says that a series of SEMI standards set for release in 2004 covering equipment data acquisition and run-to-run control could help overcome challenges posed by equipment problems, particularly with leading-edge tools.

• There are at least five major differences in the metrology chapter of this edition from previous iterations. Two of the differences: The roadmap's FEP and process integration, devices, and structures sections detail "the latest ideas on the progression from CMOS to nonclassical CMOS to post-CMOS devices. The lack of definition of the device of the future...increases the risk involved in developing new metrology tools." Another: the need for metrology for transistor fabrication with metal gates.

Predicting materials characterization remains an elusive metrological goal, notes Alain Diebold, editor of the metrology chapter and a senior fellow at International Sematech. The industry measures more properties during R&D than during manufacturing, he says. "One example may be the pore-size distribution for low k. Chances are that pore-size distribution will be measured during its initial use in a manufacturing line, but the industry may find that it has much better control of this property or develops a robust process as its use matures. We will not know the answer to this question for some time." Diebold also cites the lack of tools for detecting copper voids and killer pores in porous low-k material as problematic. —JC

The 2003 ITRS is available at http://public.itrs.net.