Moslehi, PhD, is chief technology officer and senior
vice president, semiconductor technology research, for the Noblemen
Group (www.noblemengroup. com), a boutique investment banking, strategic
advisory, and business development firm based in San Diego, Silicon
Valley, and Portland, OR. Moslehi has some 20 years' experience working
in the semiconductor and semiconductor equipment industries, including
stints with Hewlett-Packard, VLSI Technology, Philips, National Semiconductor,
Fairchild Semiconductor, Applied Materials, KLA-Tencor, and Mattson.
He can be reached at email@example.com.
past few years have seen virtually all aspects of the semiconductor
industry undergo unprecedented transformations. Rapid change has always
driven—and will continue to drive—the chipmaking world,
a place where everybody is hard at work trying to obsolete what they
have just created and introduced to the market.
current trends represent an unprecedented confluence of many fast-paced
fundamental changes that encompass both technology and business and
have taken place over a relatively short time. Timing (implementation
target dates) and latency (time to objectives) are essential elements
in the equations that define and govern these trends, with direct impacts
on cost, profit margin, and return on investment. The complexity and
multitude of these transformations, together with the need for astronomical
levels of investment and innovation, all over a relatively short time,
present numerous challenges and create a very-high-risk business environment.
roadmaps have long played a critical role, especially since the 1990s.
Yet some unrealistic roadmaps have compounded the
difficulties of timing and latency, disrupting any meaningful planning
strategies. Traditionally, technology has been the main engine propelling
the semiconductor world but, more than ever before, market forces and
economics have emerged as equally critical factors. Of course, technology
is still essential for staying in the game; however, a technology-centric
focus could become a recipe for disaster.
to manage risks and to reduce the chances of failures, a heavy dose
of reality must be injected into the decision-making process, and various
directions and options must be much more carefully studied. Fact must
be separated from fiction, and solid practical solutions distinguished
from marketing hype, so that costly and unnecessarily complex, tortuous
paths can be avoided. A multitude of recent experiences with difficult
technology transitions—such as the failure of low-k integration
at the 130-nm node and the premature introduction of 300-mm fab technology—and
vexing business challenges call out for a serious reality check.
feature is the first installment of a new column in MICRO called
Reality Check. In this space, I will examine and analyze the major changes,
transitions, and transformations that are under way in the semiconductor
industry. I will highlight how the intertwined and inextricable nature
of technology and business, combined with the realities of the marketplace,
must guide the development of aggressive yet practical technology roadmaps
along with optimized, business-savvy economic implementation strategies.
major technology transitions include the continuing move to copper/low-k
interconnect, the introduction of 90- and 65-nm design rules using subwavelength
lithography, and the widening implementation of high-volume 300-mm manufacturing.
The entirely new copper/low-k interconnect architecture, based on the
damascene process, is designed to enhance chip performance and reduce
cost. However, this transition has proven to be very difficult and costly,
particularly the integration of low-k dielectrics; in fact, low-k integration
at the 130-nm node has been generally characterized as a failure. Consequently,
the implementation of low-k materials has been pushed out by at least
two nodes from the original roadmap plans.
integration and yield issues continue to challenge the industry in the
90- and 65-nm technologies. Furthermore, the increased application of
advanced process control (APC) methods, especially in critical manufacturing
steps, is needed for managing shrinking process windows.
the industry's most important and expensive technological challenge
remains lithography. Subwavelength lithography has enabled the patterning
of feature sizes far below the wavelength of the laser light source.
This high-cost endeavor has been made possible through major advancements
in tools and materials technologies, such as scanners, tracks, reticles,
resists, and metrology. Optical proximity correction, phase-shift masks,
and other optical extension techniques have delivered impressive technical
results. Yet these achievements have been accomplished at great expense:
the exponential rise in mask costs has major implications on the economic
viability of advanced low-volume products.
lithography (NGL) may address some of these issues, but the immaturity
and prohibitive price tag of many current NGL candidates point to even
more possible showstoppers in the future. This is particularly true
for small and midsized semiconductor companies, whether they're integrated
device manufacturers (IDMs) or fabless, that do not command a high market
share or have a high product mix.
daunting complication is the lack of a real industrywide consensus on
which lithographic technologies to adopt. Perhaps the emergence of immersion
lithography (IML) will provide an evolutionary, practical solution over
the next few nodes. However, this "wet" approach is quite new and unproven
in the field: IML was not even being seriously considered up until early-to-mid-2003.
The expected success of the immersion alternative may serve as yet another
clear example that even successful evolutionary changes require huge
amounts of time and effort.
with historical industry trends, requirements for lower costs and higher
productivity have primarily driven the transition to 300-mm wafers.
The full factory automation taking place in 300-mm fabs will allow implementation
of true facilitywide integrated yield management and APC systems. The
300-mm fabs of the future will be significantly different from those
we know today.
the move to a larger wafer size makes sense for cost-productivity reasons,
the premature transition to 300-mm technology has resulted in yet another
expensive and difficult new technology introduction.
to the challenges facing the semiconductor world are a number of new
technology transitions on the horizon that will primarily focus on the
front end of the fabrication line, including transistor architecture
and design. These innovations include the use of new substrates (silicon-on-insulator,
strained silicon, silicon germanium, etc.), implementation of high-k
gate dielectric/metal gate electrode, nickel silicide, and increasingly
aggressive ultrashallow junctions. Most of these technology changes
are accompanied by the introduction of new materials, tools, and processes.
electroplating, copper CMP, copper electropolish, MOCVD, atomic layer
deposition, flash-lamp anneal, 193-nm immersion scanning lithography,
and supercritical fluids are just some of the recent or emerging production
technologies. Other new materials and processes will be introduced through
novel devices, such as the long-awaited universal memory chips (MRAM,
FeRAM, and maybe PRAM). Whatever direction it takes, the industry will
again be expected to go through a rapid learning curve with the associated
high costs and risks.
have been many significant changes under way on the business
side as well, including end-market evolution, the rise of outsourcing,
escalating R&D and manufacturing costs, and an increase in alliance
and joint-venture activities. The severity of the prolonged downturn
experienced through the recent cycle has fundamentally affected the
industry, with the potential for more consolidations and the need for
new business models. The end-markets for many systems containing microchips—PCs,
cellular phones, digital entertainment gadgets, and automotive applications—have
been progressively evolving into the commodity consumer domain. Consequently,
characteristics of these markets such as average selling-price pressures,
shorter product life cycles, consumer confidence fluctuations, and macroeconomic
factors will play increasingly important roles in managing semiconductor
outsourcing model has led to the gradual disintegration of the
traditional vertically integrated operations and the emergence of the
Asia-Pacific region as the world's high-tech manufacturing hub. Wafer
processing, test, assembly, packaging, and, more recently, design have
all been outsourced, adding strength to the fabless and foundry sectors.
dampen the effect of the business cycles and to reduce costs and capital
expenditures, many IDMs have adopted a "fab-lite" strategy, relying
increasingly on outsourcing solutions. China's emergence, both as a
budding semiconductor manufacturing center and a voracious consumer
of ICs and other chips, promises to have further serious business implications
for the global electronics marketplace.
the course of the year, I will apply the Reality Check to the important
issues I've mentioned here, as I try to bring some perspective to the
myriad of tough issues facing the semiconductor industry. I hope you
enjoy and benefit from these observations and analyses. In the meantime,
have a happy and prosperous 2004.
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