'Round The Circuit

ISMT forms new consortium

In a move that it says will help semiconductor manufacturers reduce their per-wafer and per-die costs, International Sematech has formed a new consortium. The subsidiary, called International Sematech Manufacturing Initiative (ISMI), is wholly owned by the parent consortium and operates from ISMT's Austin, TX, headquarters, with its own employees and participating companies. It began operations January 1.

"Our aim is to create a global alliance of the world's major semiconductor manufacturers," explains ISMT president and CEO Mike Polcari, "focused exclusively on manufacturing effectiveness, to reduce the costs to produce finished wafers and chips, and to drive the big productivity challenges of the future, such as the next wafer size." ISMI will have programs for equipment and fab productivity, ESH, and metrology, with a set of additional councils in manufacturing methods, yield, and supplier relations. Projects under way include e-manufacturing, spare parts management, defect sourcing, life-cycle assessment, resource conservation, and manufacturing operations analysis. Future projects could include "plug-and-play" strategies for minimizing tool installation and qualification.

"Both existing International Sematech member companies and new ISMI participants will derive benefits from improved fab productivity, thanks to a broader benchmarking sample of the world's best fabs," says Hans Stork, senior vice president of Texas Instruments and ISMT board member. "The industry will benefit from a new consortium that speaks with a common voice to help guide global suppliers and standards organizations in best meeting the industry's needs."

EUVL process simulated

An enhanced software package simulates the entire extreme-ultraviolet lithography (EUVL) process, including the printability of mask defects. Munich-based Sigma-C says that its upgraded SOLID-EUV 1.3 can create virtual, defective multilayer blanks. The EUV mask model produced from the defect-ridden blank can assess whether mask defects will print on the wafer itself and then be used to further investigate how to eliminate such defects. The availability of defect-free masks, including the development of the requisite detection and repair tools, has been cited as a critical step in EUVL technology commercialization. The software also simulates other EUVL process stages, including layer deposition, pre- and postexposure bake, exposure, and resist coating and development. It allows users to analyze processes by providing resist profiles and aerial images of the exposed, resist-coated wafer surface. The company says it has already begun shipping version 1.3.

NIST x-rays defects

Researchers recently demonstrated the feasibility of adapting small-angle x-ray scattering (SAXS) for characterizing nanometer-scale structures on IC-like samples. The team, led by National Institute of Standards and Technology (NIST) scientists, conducted proof-of-concept experiments on Argonne National Laboratory's advanced photon source synchrotron. The work focused on SAXS's ability to determine the average size of periodically repeating features that are arrayed on three chemically different samples designed to resemble mask patterns. The technique demonstrated its high-throughput potential by gathering data over a 40-µm area within a second, with precision levels better than 1 nm, according to the research group. The images amassed from x-rays deflected by electrons in the samples produced highly accurate measurements of spaces, linewidths, line-edge roughness, and feature geometries.

NIST's Ronald Jones says that technical implementation of the SAXS methods may become easier as feature sizes decrease. He believes the technique could be used for 3-D analyses and for evaluation of subsurface copper interconnects that link chip components. SAXS can also be employed to measure nanoscale devices made with inorganic or organic and insulating, conducting, or semiconducting materials.

In other NIST news, the institute has released the latest Standard Reference Materials Catalog. Featuring more than 1300 metrological reference materials, the publication is used in industrial materials production and analysis, environmental analysis, and basic scientific and metrology measurements applications. The catalog lists the reference materials with carefully assigned values for chemical composition and physical properties. To receive a copy, log on to www.nist.gov/srm or e-mail srminfo@nist.gov.

True low-k discovered

Samples of ATI's Radeon 9600 XT visual processor made by TSMC were found to use a true low-dielectric process, according to recent tests run by Chipworks. Employees of the Ottawa, ON, Canada, reverse-engineering services firm examined the devices and found them to be manufactured in a 130-nm process, with eight levels of copper and Applied Materials' Black Diamond low-k material used to isolate the lower six levels and with fluorinated glass (FSG) employed for the top two metal layers. "[We] have been trying to obtain true low-k parts for over a year, but each time we analyzed a leading-edge chip, we found FSG in there," explains Dick James, Chipworks' senior technology analyst. "This is the first chip that [we have] seen with significant structural changes that indicate the use of a 'true low-k' dielectric... a layer with a dielectric constant of 3.0 or lower."