Applied touts low-k progress

Tremendous challenges," "numerous roadblocks," "trashed schedules"—those are just some of the colorful expressions that have been used to describe the difficulty of integrating low-k dielectric materials into IC manufacturing processes. Last spring, after intensive R&D efforts, reams of conference papers, and raging debates between advocates of the spin-on dielectric approach and chemical vapor deposition technology, a host of companies announced that they were beginning volume shipments of chips incorporating low-k. Agere Systems, LSI Logic, Motorola, TSMC, Texas Instruments, IBM, and UMC all reported that they were manufacturing—or were on the verge of manufacturing—IC products with low-k dielectrics at the 130-nm and even the 90-nm nodes.

To great fanfare, Applied Materials gathered the press and analyst communities in San Francisco in early February to tout its own low-k accomplishment—the beginning of the low-k era in chipmaking, in the words of a company press release. Well, not quite. The announcement that Agere, Altera, AMD, ATI, LSI, NEC, Toshiba, and TSMC are using Applied's Black Diamond low-k film in volume production did not signal a sudden breakthrough, but rather a summation of years-long work.

Low-k capability is already "in huge production," noted Mike Splinter, Applied's president and CEO, at the February briefing. Adopting it "is a risk, is hard." Joining him at the podium were spokesmen from fabs and foundries that use Black Diamond. John Yue, technology vp of TSMC, stated that low-k makes better chips, from transistor placement to architecture. The foundry, which qualified its 130-nm low-k process in 2002, shipped 10,000 low-k-based wafers manufactured at the 130-nm node in 2003 and is beginning production of 90-nm low-k products on its 300-mm lines.

Ronnie V. Vasishta, vp of technology marketing at LSI, remarked that his company has been working with low-k films since 1997. The technology, he said, "enables getting smaller die sizes and keeping lines closer together without buffers," leading to a performance improvement of 20%.

While low-k dielectric has been adopted at the 130- and 90-nm nodes, it will continue to pose daunting challenges as the IC industry transitions to smaller design rules as outlined in The International Technology Roadmap for Semiconductors. "The integration of low-k has largely been solved," remarked David Bennett, AMD's director of strategic equipment technology and alliances, at Applied's San Francisco celebration. "Now the challenge is the thinning of the films." To achieve smaller design rules, he stated, the industry must reduce the k-value of the interconnect material from the current 3.0 level of Black Diamond to 2.4.

Addressing that challenge, International Sematech's Andreas Knorr emphasized in a telephone interview that the 65-nm node will require a material with an effective k-value of 2.7—including all layers in the stack. Today's layers, he noted, have k-values of 4.5 to 5.5, "which will not get to an effective k-value of 2.7 easily. You'll end up with 3.0 or 3.2." At the 45-nm node, "it is clear that the use of higher-k assist
layers will not be acceptable anymore. You'll have to maintain low-k assist layers in order to get a chance to reach the k-effective target."

AMD's Bennett noted that lower-k values means higher porosity. For example, a film with a k-value of 3.0 has perhaps a 15–20% porosity level, while a film with a value of 1.4 has a 50% porosity level. "Porosity leads to several problems," remarked Knorr. "It creates free volume in the material, and you have to find a way so that copper will not diffuse into the low-k material.... The other problem is that more-porous materials are mechanically weaker—they have a lower Young's modulus and exhibit lower thermal conductivity."

In the past year, International Sematech's interconnect division has developed dielectric materials in the approximate range of 2.2 to 2.4, with higher mechanical strength than previously seen. Interesting new work, Knorr reported, has been performed to reduce pore size and improve the pore size distribution across the board. However, the emergence of such materials "may not be enough," he warned. Thus, researchers are working with liners and surface modification proposals to avoid discontinuities between a surface and the metal barrier to be deposited on top of it, because such discontinuities can result in copper diffusion.

"The problems facing low-k dielectric are still substantial," Knorr concludes. "We have to push to the next technology node, but we don't have the materials. Some manufacturers will ramp up at the lower nodes without the materials and then introduce the low-k materials later, after they're developed."—BM