INDUSTRY NEWS

Chip alliances spread

Several leading chipmakers have joined together in two separate process-development alliances. Sony and Toshiba say they will extend their 65-nm collaboration (which began in May 2001) to the 45-nm technology node, with the project slated for completion by late 2005. A team of 150 engineers from the two Japanese companies will work on the project at Toshiba's Advanced Microelectronics Center in Yokohama and Oita Operations in Kyushu. A budget of close to $180 million will be shared by the two partners. The announcement comes on the heels of Sony's recent decision to invest approximately $1.1 billion in 65-nm production, a portion of which will go into IBM's East Fishkill, NY, 300-mm fab.

Samsung has joined IBM, Chartered, and Infineon in an alliance focused on 65- and 45-nm logic process development. The partnership's work takes place at IBM's Advanced Semiconductor Technology Center in East Fishkill, with each company then transferring jointly developed processes back to its own fabs. In a separate agreement, Samsung licensed IBM's 90-nm CMOS logic technology, which the Korean company plans to integrate into its system-on-chip line.

Fairchild invests in PA fab

In a rare case of new U.S. fab activity, Fairchild Semiconductor says it will invest $143 million in its Mountaintop, PA, facility. Driven in part by what the company calls its highest booking levels in more than three years, Fairchild plans to refurbish the 200-mm fab and increase discrete power semiconductor capacity there to 1200 wafers per day. A $1 million grant for job training from the Commonwealth of Pennsylvania sweetened the pot; about 320 new positions are expected to be created over the next four years. Power chips produced at the Mountaintop fab include those with applications in the automotive, entertainment, power supply, and portable markets.

ASM buys NuTool

In a move it says should strengthen its position in the copper/low-k technology space, ASM International has agreed to buy NuTool and its proprietary electrochemical mechanical deposition technology. ASM president and CEO Arthur del Prado believes that the new acquisition's "patented solutions for planar copper deposition and removal of copper in planar fashion offer great advantages and solve many technology hurdles on the back-end-of-line (BEOL) roadmap."

The companies had experience working together during a two-year partnership looking at process integration issues in advanced interconnect. ASM owns 15% of NuTool and will acquire the remaining 85% in exchange for shares of the Dutch company's common stock. NuTool shareholders must approve the deal, which is expected to close in May.

Suppliers join hands

A string of deals has increased the interrelationships of several supplier companies. Nanometrics inked agreements with Lam and Dainippon Screen for integration of its metrology units with the toolmakers' systems. The NanoOCD/DUV 9010b film-thickness mapping module has been put into Lam's CMP tool to measure postcopper CMP erosion, oxide thickness, and residue. DNS will install Nanometrics' in-line film thickness and optical critical dimension modules on an RF3 coater-developer system in its demo lab. The Japanese equipment supplier will also offer the metrology units as standard options on its new track tool.

Semitool has licensed its initial seed-layer enhancement technology, which is used to help make copper interconnects, to Applied Materials. As part of the agreeement, Applied pays an initial license fee to Semitool, an additional fee upon commercialization, and future royalties. The deal does not include any rights to the Montana-based company's bulk-fill electroplating intellectual property.

In a design win for a major subsystems supplier, a "leading semiconductor equipment manufacturer" has chosen Advanced Energy's Apex RF power-delivery system as the default standard for its 300-mm tools. This same tool company had used AE's power-delivery units on its 200-mm tools.

ASML MaskTools and Dai Nippon Printing (DNP) have established a strategic alliance on CPL technology. CPL is a single-mask, single-exposure resolution-enhancement technique (RET) supplied by the ASML unit that claims the mask optimization product can lead to as much as a 40% increase in lithography process productivity. As part of the agreement, DNP will get an R&D license from MaskTools and develop a production-worthy mask-making process that ensures delivery of high-quality CPL masks to chipmakers with fast turnaround times.

On the materials front, Soitec has licensed its silicon-on-insulator (SOI) technology to Siltronic. The German wafer supplier will use the French-based manufacturer's proprietary SmartCut process to make advanced SOI and strained SOI (sSOI) engineered substrates, providing bonded SOI wafers to its customers in 2005. The two companies are also working on a joint program to accelerate the development of sSOI wafers. Siltronic, formerly known as Wacker Siltronic, is a division of Wacker Chemie but has announced plans for an initial public offering sometime in 2004.

X Initiative gains momentum

The X Initiative, in its efforts to provide a production-worthy diagonal interconnect architecture, has added a member and successfully tested another test chip. Infineon has joined the consortium and already fabricated a 130-nm test device. The German semiconductor manufacturer plans to continue validating additional production designs using the architecture throughout 2004, hoping to "improve chip performance, reduce overall power consumption, and cut costs," according to Infineon vice president of technology development Josef Winnerl.

A 65-nm test chip employing the diagonal-interconnect design was
recently made at Applied Materials's Maydan Technology Center. The capital equipment giant worked with Canon and Cadence on the project.

The fabrication of the device "provides further confirmation of the manufacturing readiness and scalability of X-architecture designs for future process nodes," says John T. C. Lee, general manager of the Maydan Center. "It leverages standard design, verification, maskmaking, processing, and inspection disciplines into functioning interconnect test structures."