Moving forward, there are still a lot of fine-tuning and yield optimization efforts required, as fabs grapple with the integration issues presented by low-k dielectrics, such as controlling the multiple layer stresses. Sampling of claimed 90-nm processes (taken from Sony/Toshiba, TI, Intel) would indicate that manufacturers are choosing to shrink the gate dimensions but remain more conservative on metal pitch. The typical M1 pitches observed are between 300 and 330 nm compared with the 180- to 250-nm range anticipated for the 90-nm node.

The future for the 65-nm node likely will be more of the same as copper, with low-k dielectrics, is refined and optimized. To extend the dielectric constant below the ~2.6 seen in today's devices will require another material shift to porous low-k dielectrics. Progress from published activity would indicate that these materials are still a long way from reaching production. More metal layers, perhaps up to 12 levels of metal and smaller pitches on the first few metals, will probably be seen before the 65-nm process technologies are adopted for mass production.

First, the performance of a semiconductor chip's interconnect structure is governed by two factors: its line resistance, R, and its interline capacitance, C. Capacitance is the more important of the two, affecting power, device speed, and the signal-to-noise ratio. In particular, noise becomes more critical as the operating voltage of the chip declines. As voltages drop from 5 to 3.5 to 1.2, reducing the noise becomes very important. Lowering the capacitance value can accomplish that.

Capacitance, however, can be lowered in a couple of ways, and not just by the use of low-k dielectric materials. Reducing the height of the interconnect line will also reduce capacitance. Indeed, the first two generations of copper devices at the 180- and 130-nm technology nodes used a combination approach to achieve the desired capacitance value. The metal height was reduced (compared with the aluminum interconnect, i.e., leveraging the lower resistivity of copper to reduce the interconnect height and keeping the R value constant) and intermediate-level low-k films were employed (typically FSG, with a bulk k-value of around 3.6).

So why weren't true low-k materials (k of < 3.0) used at 180 and 130 nm to reduce capacitance? Because they were not production-worthy for the high-volume production of low average-selling-price (ASP) chips. The first generation of low-k films, both CVD and spin-on, were extremely soft materials. Low-k materials are often described in terms of their bulk k-value, but for volume production applications, hardness and cracking limits—mechanical strength—are equally important. These first-generation low-k films typically had k-values of around 3.0, but their mechanical properties were poor, with low hardness (1.0–1.5 Gpa), modulus of <10 Gpa, and tensile stress resulting in a cracking limit of 2 µm. They failed when the chip went to packaging. Some very expensive packaging solutions to allow the low-k to survive were developed, so these chips found their way only into a limited number of high-ASP applications, such as microprocessors.

The second generation of low-k materials is being introduced at 90 nm. Like the first-generation films, these new films are dense, and the bulk k-value remains around 3.0. But their hardness has increased to 2.5 Gpa, a modulus of ~15 Gpa, with zero or slightly compressive stress, resulting in a cracking limit of more than 5 µm. These latest films can be used with conventional packaging without fear of device failure, opening up the market for low-ASP chips.

Third-generation low-k films will be introduced at the 65-nm node. They will have bulk k-values in the 2.7 range, but will still be dense and of high mechanical strength. The fourth-generation films will make their entrance at 45 nm and will likely be porous materials, driving bulk k-values below 2.5. Since these films will be mechanically weaker, challenges in packaging will still have to be surmounted.

The ITRS Interconnect Technology Working Groups that addressed low-k implementation through the years recognized that k-values needed to become lower as linewidths decreased. Two scenarios for low-k materials could logically be considered. One was to envision a step-function process in which k-values dropped from 4 (SiO₂) to 3, later to 2, and finally to something approximating a perfect air bridge with a k-value of 1. The second vision was a gradual reduction in k-values, for example from k = 3.0 to k = 2.8, then k = 2.6, and so on. In fact, the working groups chose the latter, and thus established the concept of "extendability" in low-k interconnect materials.

Extendability in low-k materials is a satisfying concept because we can envision the repeated use of similar materials, equipment, and processes at decreasing technology nodes—all of which removes cost and complexity from the process. However, from a chemistry and materials science viewpoint, the concept needs examination as it pertains to the methyl-substituted, silicon oxide films that are the basis for all major CVD low-k processes.

Several studies have shown that the addition of methyl or other organic substituents to silicon dioxide lowers the k-value. By increasing the organic content, a k-value of about 2.8 can be achieved. Beyond that, however, the addition of more organic content doesn't further reduce the k-value, it just degrades other properties. Making these films "extendable" to lower k-values can be done in two distinctly different ways.

In one approach, the film is rendered "low density" using chemistry and morphology to stretch and strain the silicon-oxygen and other bond angles to unusually high degrees. This can lead to k-values of about 2.5, but typically at great cost in other film properties. Such films are less crack-resistant than their thermodynamically more-favored (k = 2.8) analogs and tend to exhibit certain problems, including rapid and unpredictable wet etch rates.

The second, more publicized approach involves the incorporation of porosity into the films, which is achievable through various processing methods. Porous low-k films remain the subject of intense R&D focus and may yet demonstrate that low-k films are "extendable." However, even solid (nominally k = 2.8) low-k films retain only about 5% of the mechanical strength of SiO₂ films. The incorporation of porosity causes even this residual strength to drop dramatically. For this reason, the first generation of CVD low-k films are likely to be used from the 90-nm node to 45 nm and possibly beyond.

We have created experimental single-damascene structures with a range of dielectric spacings down to 70 nm and determined the extent of modification. Using a recently developed predictive model, how much k-value reduction a process delivers at a certain technology node compared with a reference material (such as oxide) can be determined. The model demonstrates that the current technology, which is used for the 90-nm node (OSG with k = 3.0), is not scalable to the 45-nm node and beyond. New and revolutionary technologies are needed for these nodes; otherwise, it would be better to switch back to oxide.

Current technology used for the 90-nm node is not scalable to the 45-nm node and beyond. New technologies are needed for these nodes. –Gerald Beyer

HICHEM M'SAAD (vice president and general manager, PECVD division, Applied Materials): With continued scaling, the interconnect has become a potential bottleneck in chip performance. Interconnect speed is limiting chip speed, and interconnect power consumption is causing heat management and battery lifetime issues. Meanwhile, the close wiring proximity is causing unacceptable crosstalk (line-to-line interference). Consequently, low-k dielectric development continues to be a major focus, since these materials offer the most promise in terms of impact to overall device performance.

While the move from aluminum to copper yielded a 20% speed boost, that was just a one-time gain. As the linewidths shrink, this improvement actually diminishes. However, with low-k, not only does the speed increase, but power consumption and crosstalk are reduced. What's more, we can drive down the dielectric constant in future generations of technology.

But low-k extendability remains a challenge. The mechanical strength of the film needs to be maintained while lowering the k-value, all without changing the tool set. Moving to more-porous films is clearly the trend, but understanding how to work with these materials is where the real complexities begin.

The copper/low-k integration scheme is also an area of intense concentration. All interfaces between the dielectric layers must be fully optimized, requiring the use of in situ wafer-surface treatments that enhance interfacial adhesion without sacrificing throughput.

Many of the existing integration workarounds will no longer be viable; for instance, the incorporation of capping layers to compensate for weak low-k materials will have an increasing, negative impact on capacitance reduction as geometries scale. This essentially means one thing: low-k films must be robust and fully compatible with downstream processes.

Ultimately, the winning strategy for next-generation low-k development and implementation will favor the further extension of PECVD technology because of its demonstrated extendability, CVD-enabled interface control for improved BEOL reliability, and the cost-of-ownership benefits obtained by leveraging an existing installed base.

Paired with this is the nature of the back-end process interaction with the layout and performance aspects of the product. One of the biggest issues is related to how the back-end interconnect model is derived and verified. Local environments that had little or no effect at 180 nm dominate the scene at 130 nm and below. A related issue is how to measure the critical parameters in the back-end interconnect flow. Current critical-dimension SEMs are barely adequate for the task, and the multiple films and how they relate to sheet resistance compound the film measurement issue. The main process-to-design interaction relates to the ability to control not only the feature width but also the depth. The electromechanical and stress reliability of vias is directly related to the via height and barrier step coverage.

Finally, as if all of the above factors were not enough, how do you ensure that the defect level of all that back-end processing does not produce low yield by having high defect density? The standard optical scanning tools are out of gas with respect to resolution, while the advanced (and I use that term lightly) E-beam inspection tools are either too slow (read expensive) or have abysmal uptimes and at their best run at very low units per hour.