Norbert Kappel and Keith Best, ASML

With the increasing use of integrated circuits in all aspects of everyday life, including in consumer products such as televisions, cameras, cell phones, and automobiles, it is imperative that the cost of manufacturing devices be kept as low as possible. In order to reduce costs, a variety of manufacturing strategies are employed. One strategy is to use the appropriate equipment for each processing step. Fabs do not make chips using equipment that has significantly tighter specifications than required and would be therefore more expensive than necessary.

In the case of photolithography, many fabs use a mixed set of equipment. To achieve the lowest cost of operation per layer, they often expose one layer on one piece of equipment and other layers on other pieces of equipment. That strategy is especially pursued in the fabrication of many non-leading-edge process technologies, where manufacturing costs have a significant impact on the bottom line. Another important strategy is manufacturing flexibility—in other words, the flexible use of any system belonging to a family of similar tools. Whether a fab uses a mixed set of tools to expose different layers or different systems that resemble one another, optimizing the performance of an entire toolset can play a major role in semiconductor manufacturing.

This article describes a methodology that was used to plan, measure, and, where possible, correct critical parameters affecting the total overlay performance of a mixed set of lithography tools at Fairchild Semiconductor's manufacturing facility in Bucheon, South Korea. The methodology involved the characterization and fingerprinting of five Micralign exposure tools from ASML (Veldhoven, The Netherlands). Characterization wafers were processed and measured on an ASML PAS 5500 stepper. Based on data gathered in this analysis, the article describes and evaluates several methods that were undertaken to improve manufacturing, and concludes with a discussion of proposals for future improvements.

Exposing the Wafers

Lithography Tool. The Micralign is a 1X scanning projection aligner with resolution capabilities of 1 µm and below. Using broadband illumination, the large-ring field scanner exposes an entire wafer in one scan, providing both a large field size (135 X 150 mm) and high throughput (100 wafers per hour). Because of the tool's low-optical-distortion characteristics and automatic magnification compensation capabilities (overlay ≤0.3 µm), it can be easily mixed and matched with reduction stepper systems. In fact, in the metrology portion of this project, a 5X-reduction stepper was used.

Wafer and Reticle Layout. A test reticle based on multiple 22 X 22-mm fields was designed for the scanning projection aligner by ASML and Benchmark Technologies (Lynnfield, MA). A 1X full-wafer reticle, it consists of various alignment marks, including Micralign automatic fine-align marks and an ASML overlay alignment mark array used to perform metrology. The reticle and all relevant technical information files were sent to the customer fab. Wafer and reticle layout maps are presented in Figures 1 and 2, respectively.

Figure 1: Wafer map used in the experiment.

Experimental Procedure. Several aligners at Fairchild's Bucheon fab were used to expose 5-in. silicon wafers under standard processing conditions using the special 1X full-wafer reticle. The reticle pattern contained ASML primary markers for both the zero, or reference, layer and the first imaging layer. The primary markers specified a coordinate position of x = ±45 mm and y = 0 mm.

To make the patterns permanent, an etch step was performed to transfer them to the wafer substrate. A minimum of two wafers were produced on each tool. The wafers were then sent to ASML's process integration laboratory in San Jose to measure how much each wafer deviated from a nominal coordinate standard. That standard had been established for ASML's PAS 5500/150 5X reduction stepper and was used as the reference for all subsequent measurements from wafers processed on the aligners. These measurements provided an indication of each aligner's calibration state and how well each aligner would perform after being adjusted.

Figure 2: Layout of the 1X full-wafer reticle used in the experiment. Not all fields are shown.

Performing Metrology

To quantify the tools' prealignment matching offsets as well as within-tool and tool-to-tool overlay performance, the metrology portion of this project used a PAS 5500/150 stepper with a specified resolution of 0.35 µm. The stepper's standard field size is 22 X 22 mm.

After the wafers had been received from the customer with the etched primary markers and overlay layer 1 pattern, each tool's prealignment capability—i.e., the ability of the wafer to move from the wafer cassette to the exposure chuck—was determined.

To quantify prealigner matching offsets, wafer coordinate system (WCS) and geometric wafer coordinate system (GWCS) offsets were measured on the patterned wafers using the stepper's mark sensor. The WCS uses the marker on the wafer to locate the aligner pattern, while the GWCS senses the wafer edge and determines the geometrical center of the wafer. The WCS performs standard prealignment by determining the difference between aligner-pattern positions from one wafer to another. Results of this determination are presented in Table I.

Aligner Wafer ID WCS Offset Offset x (mm) WCS Offset Offset y (mm) Rotation (°) 1 14 –0.088 –0.494 0.2578 1 24 –0.086 –0.497 0.2571 Delta 0.002 0.003 0.0010 2 23 0.238 0.494 –0.2368 2 20 0.238 0.495 –0.2343 Delta 0.000 0.001 0.0030 3 12 0.240 0.493 –0.2423 3 16 0.347 –0.235 0.1575 Delta 0.107 0.728 0.4000 4 2 –0.127 0.494 –2.4210 4 3 –0.123 0.449 –2.4250 Delta 0.004 0.045 0.0040 5 21 0.040 –0.402 0.4220 5 18 0.196 –0.412 0.3775 Delta 0.156 0.010 0.0450

Table I: Prealign matching offsets.

The second step in the metrology procedure was to measure the printed aligner pattern. Using the alignment and metrology features of the reduction stepper, the position of each marker printed by the aligner was measured against the absolute position of the stepper stage.

Before the final overlay data set was measured, the WCS offsets for x, y, and rotation presented in Table I were corrected in the metrology system for each set of wafers. The corrected values represented each aligner tool's prealigner offsets.

The overlay data set was measured on the stepper in test manager mode. The results of these measurements are summarized in Table II. Nine 22 X 22-mm fields were measured on each wafer. In each field, an array of 11 X 11 measurements were taken, resulting in 121 data points per field. Consequently, more than 1000 data points were measured per wafer. Table II clearly indicates that the aligner wafers performed well within a range of 250 nm, assuming that all specified corrections could be made.

The results of the correction process can be displayed in vector plots showing x and y displacement between the aligner grid and the stepper reference grid. The vector plot shown in Figure 3a presents overlay values before corrections were made, while the improved vector plot in Figure 3b presents the same data after all known corrections were made.

Figure 3: Overlay performance (a) before and (b) after corrections were made to the aligner.

Test Results

Given the matching capability and setup of the alignment tools' prealigners, all wafers, with the correct offsets, could be captured and measured using the reduction stepper's mark sensor. An analysis of the delta data from the prealignment step indicated that aligners 1 and 2 provided the best repeatability.

Given the tools' specifications, measurements of field/grid mark positions gave reasonable results. The largest contributors to overlay error were nonorthogonality and y scaling, which could have been introduced by the aligners' scan-scale and scan-skew setup errors. The metrology approach discussed here clearly demonstrated that the stepper can characterize the aligner's x, y image distortion against an absolute grid. The aligners' overlay performance can be improved if the scan skews and x and y magnification are optimized using a company-specific reference grid.

The aligners' wafer-to-wafer consistency was very good, showing that tool performance is repeatable and well within specifications. Based on modeled overlay data, each tool can perform at the 250-nm level or better after being adjusted.

The data set presented here represents a single scan and is, therefore, only a distortion measurement. True overlay performance also involves marker capture and alignment tolerance errors. However, since these errors were not measured, they have not been included here.

Conclusion

From this analysis it is clear that the aligners were performing within customer specifications and could be employed in a flexible manufacturing environment. Further performance improvements can be achieved by recalibrating all systems using an improved grid (optimized according to the company's absolute grid) as a reference.

If resolution or overlay performance beyond the capability of the aligner is required, existing aligners can be mixed and matched with 5X-reduction stepper systems. In addition to its greater lithographic capability, the stepper offers onboard metrology capability that can function as an in-house resource.

Another significant advantage of the mix-and-match approach is that existing metrology can be used to characterize not only the aligners over a complete fabrication area, but also nonlithographic process tools such as furnaces, which can cause thermally induced wafer distortion.

The key to minimizing the cost of lithography processes is to use and optimize existing equipment sets if they fulfill all the technical requirements of producing IC patterns. The results of the metrology experiment discussed in this article prove that the Micralign systems fulfilled those requirements at Fairchild's semiconductor fab in Bucheon.

Acknowledgments

The authors wish to thank the lithography staff of Fairchild Technologies, South Korea, for supporting the characterization experiment presented here. Furthermore, they would like to thank Patrick Reynolds of Benchmark Technologies for his support in designing and manufacturing the 1X reticle used in this experiment. Finally, they acknowledge Alexander Friz, Binder Mann, Jim Masterson, and Rodney Chisholm of ASML Special Applications for their lab and logistics support.

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Norbert Kappel joined the special applications group of ASML (Veldhoven, The Netherlands) in 1998 as head of marketing. In that capacity, he is responsible for developing new business opportunities in special applications markets. Previously, he held several lithography engineering and development positions at semiconductor and thin-film-head companies, including Intel, IBM, and Headway. He received an MS in chemical engineering in 1983 from Friedrich Alexander University in Nuremberg, Germany. (Kappel can be reached at 408/719-6382 or norbert.kappel@asml.com.)

Keith Best is director of worldwide process integration laboratories for ASML's special applications group. He has more than 18 years of semiconductor experience in various process engineering and applications roles. He received a BS (Honors) in materials science from the University of South East London, UK. (Best can be reached at 408/719-6375 or keith.best@asml.com.