edition includes no surprises, sets stage for 2005
expected, no surprises lurk in the 2004 update of the semiconductor industry's
technological guidebook. The 14 technology working groups reviewing the
document determined that the 2003 version of the International Technology
Roadmap for Semiconductors (ITRS) correctly assessed the
industry's challenges and technological requirements. The incremental
changes made in the latest update set the stage for the complete revision
of the 2005 roadmap.
EMERGENT: An overview of the emerging research devices chapter
of the ITRS's 2004 update "illustrates the relationship
of particular new concepts to the four functional categories that
they each address."
update notes that critical dimension (CD) control tolerances, the timing
of the introduction of the 450-mm wafer size, and the necessity of improved
yield models that include new materials are among the challenges facing
the industry. The document also cited the need for new high-aspect-ratio
inspection systems and improved data management for yield learning.
significant change is the inclusion of all 15 years on the ITRS
timeline. The addition of 2011, 2014, and 2017 means that the roadmap
now features technology requirement parameters for each year, explains
Peter Zeitzoff, a Sematech senior fellow active in the process integration,
devices, and structures (PIDS) technology working group (TWG). The 2003
and previous versions of the roadmap contained technological specifications
for only the short-term years—defined as the first seven years from 2003
through 2009. The segments of the map covering the long-term years specified
challenges for six years up to 2018, but skipped 2011, 2014, and 2017.
The updated document no longer has these gaps.
are other highlights in the 2004 edition:
The participants revised 128 of the 219 tables in the ITRS, added
four tables, and updated 12 figures.
Several chapters include new topics. In particular, a section on emerging
research materials has been added to the chapter on emerging research
The low-k section of the roadmap remains unchanged for the first time
in 10 years.
Copper resistivity numbers are now included in the interconnect chapter
to take into account surface- and sidewall-scattering effects.
The yield enhancement chapter notes that edge exclusion is spread among
that chapter as well as the chapters for front-end processes, lithography,
and factory integration because of edge exclusion's importance to defect
detection and characterization.
obtained from participants in several key wafer-processing TWGs reveal
the extent of the work that continues, both literally and figuratively,
in the trenches. In the metrology chapter, the working group singled out
CD measurement technology as an important new message.
Diebold, a Sematech senior fellow and TWG participant, says the determination
is supported by an SPIE conference presentation by Bryan Rice of Intel
and by a report on scatterometry to the working group by Dan Wack of KLA-Tencor.
Wack's "careful study" showed the impact of extending scatterometry to
shorter wavelengths, while Rice's report showed CD-SEM and scatterometry
of isolated lines measuring 16-nm wide with a 1:10 pitch as well as 36-nm
nested lines with 1:3 and 1:1 pitches, Diebold points out.
could resolve the line edges, and scatterometry and CD-SEM correlate well
with each other," explains Diebold. "The need is for improved instrument
performance so that a higher precision is achieved."
metrology working group limns five difficult challenges at the 45-nm technology
node or greater through 2009 and five difficult challenges beyond 2009
at nodes smaller than 45 nm. One key short-term obstacle for all metrology
methods is the control of high-aspect-ratio technologies such as damascene
processing. Group members note that the industry has yet to establish
new process control requirements. In particular, they point out that 3-D
measurements will be needed for trench structures in processes using low-k
believes the industry is taking steps to address the issue. "The latest
CD-SEMs have tilt capability," which permits the measurement of line shape
and the ability to look down contact holes. He says the big challenge
"is determining contact-hole dimensions in dual damascene."
summary of challenges emphasizes that standards institutions such as the
National Institute of Standards and Technology (NIST) must have rapid
access to advanced development and manufacturing capability in order to
develop the appropriate reference materials. Diebold says electron-beam
lithography "is being pushed to its limits, and most places do not have
access to a state-of-the-art system."
stresses that National Science Foundation/National Nanotechnology Infrastructure
Network (NSF-NNIN) facilities in the United States do have "this type
of capability. For example, Cornell [University] has a new E-beam system."
ATDF, a subsidiary of Sematech, offers fabrication of 300-mm wafers, Diebold
PIDS chapter features only minor changes from 2003. Among the most difficult
challenges through 2010 at 45 nm and larger are the cost-effectiveness,
process control, and reliability of very thin oxy-nitride gate dielectrics.
Specifically, the summary says that the gate dielectric will be unable
to meet gate-leakage current limits by 2006. Sematech's Zeitzoff points
out that this inability applies only to such applications as low-standby-power
and low-operating-power logic devices, "where the leakage current specifications
are low, and it is absolutely critical to meet them. For high-performance
logic, silicon oxy-nitride gate dielectric is projected to be able to
meet the gate-leakage current limits until 2007.
industry's preferred approach to dealing with this issue is to implement
high-k gate dielectric stacks, which have a greater thickness than oxy-nitride
gate dielectric for the same equivalent oxide thickness," Zeitzoff continues.
"As a result, if the high-k dielectric has a sufficient energy barrier
relative to silicon, the gate-leakage current will be lower for the high-k
well will process integration teams cope with materials, process, and
structural changes coming at such a rapid clip? Zeitzoff says it's unclear
whether the industry will meet the projected deadlines for the potential
solutions in the PIDS chapter. The PIDS group believes the introductions
of the most critical innovations will follow this schedule: strained silicon
for enhanced channel mobility, 2004; high-k gate dielectric for low-power
logic, 2006; metal-gate electrode and high-k gate dielectric for high-performance
logic, 2007; ultrathin-body, fully depleted (UTB-FD), single-gate silicon-on-insulator
(SOI) MOSFETs, 2008; and UTB-FD multiple-gate MOSFETs such as FinFETs,
requirements will control the timing of these innovations, Zeitzoff points
out. Current "solutions" considered inadequate to meet technological requirements
are shown in the roadmap with projected timelines for the appropriate
innovation needed to overcome the problem. He emphasizes that the timing
of the innovations "is meant to represent the leading edge of the IC industry
as a whole."
transistor scaling with its varied parameters is complicated, the industry
will need to use "workarounds" for innovations that prove unworkable in
their projected introductory year, the Sematech senior fellow says. "For
example, if high-k gate dielectric is not available for deployment in
2006 as projected, then one approach would be to slow the scaling of EOT
[equivalent oxide thickness] to meet the gate-leakage current limits even
with oxy-nitride. To compensate, some of the other parameters, such as
source/drain extension junction depth and the mobility enhancement from
strained-silicon channels could be scaled more aggressively."
insists that the industry has had good success at meeting these challenges,
although the timing of the solutions is difficult to predict accurately.
Notably, chipmakers are already using strained silicon in their processes
according to projections. Nevertheless, "each of the other innovations
has significant technical challenges remaining, including ensuring reliability
two factors, along with cost, are also major components in the factory
integration focus area. "Factory integration plays a critical role in
ensuring that our factories and enterprise systems are designed and integrated
to enable process development and high-volume manufacturing so that the
right products are made in the right volume on schedule with high yield,
while meeting cost targets," says Mani Janakiram, cochairman of the factory
integration TWG and a manager for analytics and visualization at Intel.
may have to turn to improvements in fab productivity, having wrung as
much cost savings as possible from advancements such as reductions in
feature size and near-perfect yields. Reaching the next level of cost
efficiency requires breakthroughs in factory design and manufacturing.
Janakiram attributes significant decreases in cost per function to these
advancements, but he notes that much more cost reduction "is expected
through improved factory design, system integration, and overall factory/enterprise
and his TWG say the industry must focus on three priorities: airborne
molecular contamination (AMC), conversion to the 450-mm wafer size, and
proactive visualization. AMC's impact will be most severe at the 45-nm
node, because "it could be a potential technology barrier and yield limiter,"
he points out.
Intel manager notes that it took the industry more than nine years to
"fully migrate from 200 mm to 300 mm, and it is now reaping the benefit
of approximately [a] 30% improvement in cost. The same is expected from
migrating to 450 mm." Because the roadmap projects the conversion to become
effective in 2012, the industry must begin its assessment and analysis
now, he insists.
visualization takes into account "the interdependence of all facets of
semiconductor manufacturing," he says. The concept gives IC manufacturers
"a seamless and transparent view" of a fab's information flow so that
they can make production decisions based on good data.
the past decade, the importance of the environmental, safety, and health
(ESH) area has grown significantly. Among the key ESH challenges cited
in the 2004 update are the need for quality rapid assessment methodologies
for new chemicals and the need to design energy-efficient process tools.
Jewitt, chairman of the ESH working group, joined the team when it first
formed in the early 1990s. He defines new chemicals as any "not being
used today." The roadmap also defines advanced photoresists and high-
and low-k materials as examples. Researchers need "some preliminary indications
of ESH properties on potential candidate chemicals that do not already
have sufficient ESH information."
Worth, a Sematech fellow and ESH working group member, says examples of
new materials include salts to raise the refractive index of fluids for
193-nm immersion lithography and chemicals such as hafnium and hafnium
compounds for high-k processes. Methodologies could include supplementing
data on material data safety sheets with a search of Internet databases
and other resources in order to compile a matrix with approximately 75
ESH data types, he notes. Characterizing emissions from tools using the
new materials is another potential method for rapid assessment.
long-term ESH challenges stand out in the updated document: the need to
understand regulatory requirements that affect chemical restrictions and
the need for broad material life-cycle analysis. Jewitt says that the
industry has had great success mitigating ESH risk in chemical usage.
However, simple mitigation efforts may no longer be sufficient.
regulatory trends are for use restriction or prohibitions rather than
mitigation," he points out. "The need is to comprehend potential for future
restrictions during the early, or long-term, development of new materials,
rather than learning that a material is not usable after 10 to 15 years
of research has been completed."—JC
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