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Critical Materials

Eliminating etch-sequencing-induced dielectric defects in high-volume manufacturing

Satnam Doad, Agilent Technologies; and Abhay Ramrao Deshmukh, National Semiconductor

Semiconductor manufacturers often employ unique practices in their fab operations resulting from their operational methodology, tool configurations, and known process sensitivities. To achieve effective tool utilization, they often configure their dry-etch tools for multiple processes, such as oxide, nitride, and spin-on-glass (SOG) dielectric etch. The interaction between these varied processes and their residual effects on chamber conditions can change process outputs and generate unique defects. Because the information available in traditional books and best-known methods generally does not help solve unconventional issues, fabs must resort to extensive investigations and experimentation to formulate solutions.

This article presents a case study from National Semiconductor's fab in Arlington, TX, in which a residual contaminant from an upstream dry-etch process interacted with incoming material to produce localized spongy-looking SOG defects in a downstream interlevel dielectric (ILD). The article discusses the origin of this unique defect, the process conditions that affect it, and various methodologies that can be used to monitor, control, and eliminate it. Finally, the article analyzes the defect's effect on various electrical test parameters and die yield.

Defect Origin

In >0.5-µm devices, SOG is used extensively to perform planarization processes.1 Five steps are performed to achieve a planar ILD surface: deposition of a base dielectric, SOG deposition, SOG etch back, SOG cure, and deposition of a cap dielectric. Two types of dielectric materials are typically used in ILD processes: doped and undoped ones. Doped oxides can be obtained by adding appropriate doping gases, such as phosphine (PH3) or diborane (B2H6). The ILD scheme under discussion here used phosphorus-doped tetraethylorthosilicate (PTEOS).

In this case, an intermittent yield loss in a few lots was investigated and found to be related to metal bridging. The scanning electron microscope (SEM) cross-section images in Figure 1 show a bad wafer with metal bridging and a known good one without metal bridging. In Figure 1a, the image indicates that the bridging was caused by unetched metal steps, which in turn were caused by spongy and void-filled defects in the cap dielectric. It can be seen that these spongy cap-dielectric defects were localized—in other words, they appeared only over the SOG pockets. In contrast, no defects could be observed over the non-SOG areas. After a detailed analysis, a correlation was drawn between the occurrence of the defects and the sequencing of defect-bearing lots during the SOG etch-back step through the plasma etch tools. These lots were preceded by bond-pad etch lots.

During the bond-pad etch step, especially for big bond pads, large quantities of residual aluminum and titanium contaminant are sputtered from the underlying metal layer and deposited onto the etch-chamber walls. This contaminant is resputtered during subsequent etch processes. In the case
of the SOG etch-back step at National, it was thought that phosphorus present in the underlying base dielectric aggressively gettered that residual aluminum, depositing a thin polymeric film over the SOG pockets on the wafer. Outgassing from this polymeric film during cap dielectric deposition caused the cap dielectric to become spongy, as shown in Figure 1a. The intermittent nature of the problem could be explained by the fact that the metal steps resulting from the spongy SOG issue were sometimes small, and metal overetch was sufficient to etch it completely.

Eliminating the Spongy Defects

To eliminate the spongy defects, a standard problem-solving procedure was performed in which affected and unaffected wafers were grouped and contrasted and failure theories were formulated.

Solvent Content. The engineers observed that only the dielectric deposited over the SOG pockets was affected and that there was no commonality among the affected lots after the SOG cure step. Hence, their initial failure theories focused on the residual solvent content of the SOG. Efforts were made to recreate the defect problem by increasing the solvent content, limiting the duration of the SOG cure step, and skipping the SOG bake process altogether. However, these measures failed to reproduce the problem, indicating that it was not related to the residual solvent content of the SOG.

Etch Sequencing. After performing the solvent-content experiments, the engineers investigated the product mix by determining when problem lots had been processed relative to etch-chamber clean cycles and by analyzing the lots and processes that were run before and after the problem lots. Based on data from those tests, the investigators observed that there was no relationship between the production of problem lots and etch-chamber cleans. However, all the problem lots had been run through the SOG etch-back step immediately following the bond-pad etch process. This effect was illustrated clearly when the circuit yield for lots preceded by bond-pad etch was compared with the circuit yield for lots preceded by other processes. A comparison between the two groups, illustrated in Figure 2, indicates that the average circuit yield for the lots preceded by bond-pad etch was approximately 5% lower than that for the lots preceded by other processes.

Figure 2: Circuit yield from bad lots with spongy defects (in which the SOG etch-back step was preceded by bond-pad etch) and circuit yield from good lots (in which SOG etch back was not preceded by bond-pad etch).

Another trend investigated by the engineers was wafer quality at the beginning and end of a lot. After each successive SOG etch-back wafer was processed following bond-pad etch, chamber seasoning resulted in a decrease in the residual aluminum level in the etch chamber. This phenomenon was reflected in decreasing yield loss as wafer processing continued. Figure 3 compares the normalized yield for the first half versus the second half of a lot that had undergone the SOG etch-back process following the bond-pad etch process. Yields from the second group were demonstratively better than those from the first group.

Figure 3: Comparison between the normalized yield for the first half versus the second half of a lot that had undergone the SOG etch-back process following the bond-pad etch process.

Time-of-flight secondary ion mass spectroscopy was used to determine the aluminum and titanium concentrations. Data from a wafer that had undergone the SOG etch-back step following bond-pad etch were compared with data from a control wafer that did not undergo bond-pad etch. The aluminum level on the experimental wafer was 35 to 45 times higher than that on the control wafer, while titanium intensity was 130 to 170 times higher and titanium oxide intensity was 80 to 100 times higher.

Underlying Film Composition. First-level dielectric films use phosphorus-doped materials because phosphorus plays an important part in the gettering of aluminum. In contrast, at the intermetal levels, undoped dielectrics are commonly used. To determine the effects of doped and undoped dielectric materials on the formation of the spongy defects, the investigators compared cross-sectioned SOG pockets from wafers with a doped or undoped base dielectric that had been processed after the bond-pad etch process. The spongy defects could be seen only on the wafers with a doped base dielectric.

In-Line Process Monitoring and Control

To optimize in-line process monitoring, various inspections were performed during the process sequence. During one such inspection, a subtle shift in the carbon monoxide (CO) signal was observed, as illustrated in Figure 4. The figure compares a typical CO signal obtained from a plasma during the SOG etch-back step with the CO signal obtained from a wafer processed after the bond-pad etch process. The typical SOG etch-back signal rises steadily as more SOG is etched away and a higher CO signal is obtained from the underlying base dielectric than from the SOG. The signal flattens when most of the signal is obtained from the base dielectric. However, when SOG etch back is performed after bond-pad etch, the CO signal rises quickly, with an initial kink followed by a relatively longer flat region. This response indicates that most of the signal is obtained from the base dielectric, not the SOG. The engineers theorized that the SOG surface experiences a polymerizing reaction at that moment.

Figure 4: Comparison between the monitored CO signal from wafers that underwent the etch-back step following bond-pad etch and control wafers that did not undergo bond-pad etch.

In another experiment, the effect of when a wafer in the lot was processed was captured by monitoring the CO signal. Figure 5 compares the CO signal from the first two and the last two wafers of a lot that underwent SOG etch-back following bond-pad etch. It shows that as the residual aluminum in the chamber was depleted, the CO signal began to resemble a typical SOG etch-back signal from a good lot.

Figure 5: Comparison between the CO signal from the first two and the last two wafers of a SOG etch-back lot that was processed after bond-pad etch.

Conclusion

This article described an investigation in which ILD deposited over SOG pockets resulted in spongy defects. Experiments were performed to test a range of theories and uncover the root cause of the failure. The failure mechanism involved a complex interaction among the residual aluminum in an oxide etch chamber, the phosphorus content of underlying dielectric films, and SOG. After the root cause of the problem was pinpointed, the investigators performed in-line monitoring to control it. Interim control over the defect problem was obtained by segregating the tools that perform both SOG etch-back and bond-pad etch. In addition, the engineers investigated the use of undoped base dielectric to help solve the problem.

This work illustrates the need for caution when increasing tool utilization by using a single tool to perform different etch processes. It also highlights the increasing importance of analyzing the product mix to solve process problems and reduce yield-limiting failures.

Acknowledgments

This work was performed at National Semiconductor's Arlington, TX, manufacturing facility. The technical input and encouragement from Glen Rentschler, Chara Mathur, Steven Watson, Amber Longstreet, John Devlin, and Nihar Kanungo are greatly appreciated.

Reference

1. SR Wilson, CJ Tracy, and JL Freeman Jr., eds., Handbook of Multilevel Metallization for Intergrated Circuits: Materials, Technology, and Applications (Westwood, NJ: William Andrew/Noyes, 1993), 382–402.


Satnam Doad is an R&D engineer at Agilent Technologies (Fort Collins, CO). He has more than nine years of experience in various areas of semiconductor processing. Before joining the company, he held a process engineering position at National Semiconductor. He received an MS in chemical engineering from Arizona State University in Tempe. (Doad can be reached at 970/288-4903 or satnam_doad@agilent.com.)

Abhay Ramrao Deshmukh is a process engineer at National Semiconductor in Arlington, TX. He has worked at the company for four years in the areas of PVD systems and SOG planarization. He received an MS in materials sciences from the South Dakota School of Mines and Technology in Rapid City. (Deshmukh can be reached at 817/705-7345 or abhay_deshmukh@yahoo.com.)


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