implementation of strain engineering has brought to bear a whole new
set of techniques for scaling front-end-of-line (FEOL) structures well
into and possibly beyond the 45-nm realm. By slightly modifying dielectric
films and combining temperature, pressure, and other knob-twisting on
the process chambers of existing equipment platforms, the desired film
stresses—both compressive and tensile—can be tuned. With
what appears to be additive effects, strain engineering boosts electron
mobility without narrowing the transistor channel. A number of strain
combinations (tensile and compressive SiN, selective epitaxial SiGe,
etc.), which vary depending on the process integration schemes of the
respective companies, are already in use in many leading-edge fabs.
This issue's Hot Button presents the viewpoints of three FEOL gurus,
who explain why strain is a great way to manage stress and improve device
GHANI (integration manager, 45-nm logic technology, Portland Technology
Development, Intel): There have been frequent predictions in
the past on the impending demise of Moore's Law and the resultant halt
of technology scaling. All of these predictions have been proven wrong
in due time as the perceived barriers have been conquered through process
and device technology innovations. As a consequence, transistor gate
lengths have shrunk to below 50 nm in state-of-the-art logic production
processes. I believe that Moore's Law will continue to hold over the
next 10 years, but numerous technological innovations will be required
to maintain the pace of transistor scaling and performance gains along
top two critical issues facing front-end logic technology are: one,
addressing the significant power dissipation challenge without degrading
overall performance, and two, maintaining high drive current at scaled
voltages and smaller gate dimensions. Effective solutions to these issues
require significant modifications to the front-end process flow, including
the introduction of new strain techniques to significantly increase
channel mobility, selective introduction of new materials into the existing
silicon technology base, and eventually changing from the existing planar
transistor to a more radical nonplanar transistor structure.
strained silicon technology has already been demonstrated to dramatically
increase transistor mobility and, thus, transistor performance. It has
recently been implemented in production. It will likely be in common
use for years to come, with even higher levels of channel strain introduced
to satisfy the requirements of high drive current at lower supply voltage
(VDD) without the thinning of gate oxides (TOX).
Since defect growth under strain is faster than without strain, achieving
high levels of channel strain in production while keeping defect levels
under control will be a significant challenge. The successful integration
of high levels of channel strain has the potential to significantly
improve performance, which would delay the implementation of metal gate,
nonplanar transistors, or other more-challenging process options by
one to two generations.
are three different transistor technology innovations beyond strain
enhancements. Metal-gate electrodes reduce electrical TOX
by eliminating polysilicon (poly-Si) gate depletion. Metal-gate transistors
can be implemented either by fully siliciding poly-Si gates or by depositing
separate gate electrode metals. High drive currents have been demonstrated
for both metal-gate implementation options; however, each option has
its own unique set of process challenges. High-k gate dielectric offers
a path to TOX scaling while keeping acceptable
levels of gate-leakage power for future high-performance logic nodes.
High-k insertion is expected to be particularly beneficial to low-power
technologies where gate-leakage reduction is important for minimizing
standby leakage power.
fully depleted transistor structures such as trigates and FinFETs enable
steeper subthreshold slope and channel-length scaling. A steeper subthreshold
slope enables transistor off-state leakage (IOFF)
reduction at a given threshhold voltage (VT),
thereby reducing leakage power without undue performance penalty. The
improved electrostatics of trigate/FinFET structures will enable continued
gate-length scaling, while the low channel doping will ensure higher
mobility relative to bulk transistors at scaled dimensions. However,
mitigating a high extrinsic resistance (REXT)
caused by ultrathin body and demonstrating yield worthiness of trigate/FinFET
transistors will be a significant challenge.
PINTO (senior vice president, chief technology officer, Applied Materials):
Strain engineering has become a powerful tool in CMOS scaling. In parallel
with junction engineering, gate-oxide scaling, and poly CD reduction,
strain engineering can deliver enough of a performance boost to extend
Moore's Law for several more generations.
strain engineering, a silicon atom is displaced in its lattice by as
much as 4%. This displacement significantly reconfigures the electronic
structures of the silicon lattice to accelerate the flow of electrons
and holes, thus increasing device performance. Since electrons and holes
respond differently to the strained lattice in the channel region of
MOS devices, two types of strain-inducing films are required: a set
of films for NMOS and a set of films for PMOS devices, tensile and compressive,
challenges to implementing strain engineering are several. First, we
need to develop films of high enough stress to deliver the desired lattice
change. For 45-nm logic devices, individual film-stress requirements
are expected to exceed 3-GPa tensile and 2-GPa compressive (compare
that with conventional film stresses of 100–200 MPa). Second, these
strain-inducing films must be similar enough to films already in use
to minimize integration impact. Finally, developing these films on existing
equipment minimizes risk and cost of implementation.
engineering can deliver enough of a performance boost to extend
Moore's Law for several more generations.
families of films are being pursued in today's sub-65-nm node for stress
induction. These include nitrides and oxides that, essentially, replace
existing films with a high-stress variant. The industry is also utilizing
the lattice mismatch between silicon germanium (SiGe) and silicon.
films were among the first to be adapted for this application, coming
into use already at 130 nm. By controlling the N-H, Si-H, and Si-N bond
ratios and optimizing deposition conditions such as power and pressure,
the films' stress can be tuned over a broad range, from –3.0 to
+2 GPa. Yang et al. showed at the 2004 International Election Devices
Meeting that the stress induced in the channel by a nitride liner film
results in a >12% increase in saturation drive current (Idsat)
in NMOS performance and >20% for PMOS, respectively.
second family of films that can be used for strain engineering are the
oxides used in shallow-trench isolation (STI) and premetal dielectric
(PMD) fill. Typically, STI fill is an HDP-CVD oxide—a slightly compressive
film. However, replacing the HDP oxide with a tensile TEOS/ozone film
that undergoes shrinkage during the postdeposition anneal creates 1-GPa
tensile stresses in the channel and increases drive current on the order
of 5–10%. Adding a 350-MPa tensile PMD film further increases the
NMOS drive current by 2–6%.
SiGe can be used to induce a compressive stress when it replaces conventional
silicon source/drain regions of the transistors. This is accomplished
by etching a recess into the Si and selectively growing an epitaxial
layer of SiGe. Because the lattice constant of the SiGe is larger than
that of Si, the channel region between the two SiGe source/ drains is
placed under compressive stress. For a Ge:Si ratio of 20%, compressive
channel stresses on the order of ~1 GPa are induced, leading to drive-current
improvements of 35% for PMOS transistors.
put these drive-current increases into perspective, such currents have
normally increased by 30% in the transition from one technology node
to the next. Computer simulations show that the stresses from the multiple
films used can be additive. This leads to the exciting conclusion that
the drive-current improvements required for spanning as many as two
technology nodes can be achieved using these strain-inducing techniques.
RIM (manager, CMOS performance solutions, Semiconductor R&D Center,
IBM): As CMOS scaling continues into the 65-nm node and beyond,
physical limitations play an increasingly crucial role in determining
performance and integration density trends. Leakage current and power
density concerns limit geometric scaling of parameters such as gate-oxide
thickness and gate lengths, which have set the pace of CMOS performance
for 40 years.
engineering replaced geometric scaling as the primary performance driver
starting with the 90-nm technology node. Strain-induced carrier mobility
enhancement in silicon was first demonstrated in the late 1980s by pioneering
research groups at IBM, Bell Labs, and Daimler Labs in Si/SiGe heterostructure
experiments. In short, strain modifies the electronic band structure
of silicon and can improve fundamental carrier transport properties.
Such enhancement can translate to increased current drivability independent
of geometric scaling. So the strain benefit in MOSFET is largely additive
to the impact of conventional device scaling.
control can add another dimension to the challenges of controlling
strain is introduced into the MOSFET channel through various techniques.
The so-called global strain or wafer-level strain refers to formation
of strained-silicon substrates by utilizing the crystalline lattice
mismatch between silicon and SiGe. A number of companies have successfully
demonstrated stress-imparting dielectric layers over MOSFETs to introduce
strain into the device channel. IBM and its development partners recently
reported a technique, called dual-stress liner, to integrate separate
optimization of such layers for n- and p-MOSFETs in a 90-nm technology.
Device channels can also be strained by inserting epitaxial SiGe in
selective areas of a MOSFET, such as the source and drain.
as geometric scaling of devices enabled years of CMOS performance enhancement,
strain scaling is expected to drive performance in future technology
generations. Combining different strain-engineering techniques is a
promising prospect to maximize the benefit. For many of the FEOL process-induced
strain-engineering techniques, geometric scaling of the device can result
in more-effective coupling of strain into the MOSFET channel.
engineering also introduces some unfamiliar challenges as well. One
fundamental issue is the trade-off between strain-induced performance
and defect generation that negatively affects yield. A new understanding
of the maximum, yieldable stress level is required. Shrinking ground
rules and the effects of 3-D geometries make process modeling and device
design increasingly complex. Strain control can add another dimension
to the challenges of controlling device variability across both the
chip and the wafer. On the other hand, such challenges are also opportunities
for innovations in silicon technology. Strain is a critical feature
in today's CMOS technology and is vital for ensuring that our industry
continues driving exponential gains in price and performance.