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Comparing the costs of photoresist coating using spin, spray, and electrodeposition systems

Nga P. Pham and Pasqualina M. Sarro, Delft University of Technology; and Jurgen Bertens and Lucas van den Brekel, Besi Plating

The cost of the photoresist coating process is a major component of the cost of ownership in semiconductor manufacturing. Minimizing the volume of resist used in coating applications results in lower manufacturing costs by reducing both chemical consumption and waste disposal costs. Estimating the amount of resist consumed and understanding the parameters involved in the process help fabs to calculate the coating costs.

This article compares the costs of spin, spray, and electrodeposition (ED) photoresist coating methods, which are used to form the thick (3–10-Ám) resist layers that are often required to fabricate 3-D microstructures, radio-frequency MEMS devices, and advanced packaging.1,2 To evaluate the costs of photoresist consumed in such processes, a figure of merit is introduced that defines resist- coating efficiency. The efficiency values cited here were derived from tests on 100-mm silicon wafers. The article estimates resist costs only. It does not consider equipment- and maintenance-related costs.

Coating Efficiency

Photoresist has two main components: solids and solvent (or aqueous solution, in the case of ED resist). Only the solids contribute to the formation of resist film. They are also the largest contributor to overall resist costs. Moreover, during coating, only a portion of the resist is deposited on the wafer—the rest is wasted material. Coating efficiency (CE) is based on the amount of resist that is effectively deposited on the wafer. A schematic diagram illustrating the coating efficiency of spin, spray, and ED resist coating methods is presented in Figure 1.

CE is the ratio of resist deposited on the substrate to the total volume used. Representing the coating efficiency of each coating method, it is defined as follows:

Coating efficiency is primarily a function of the coating method or equipment used and the size of substrate. More-efficient use of materials helps to reduce manufacturing costs. In general, the CE of liquid spin coating is approximately 2–5%, while the CE of spray coating is 15–40% and the CE of electrodeposition coating is 60–95%. CE values vary depending on system design and mode of operation.

Comparing Coating Methods

Spin Coating. The greatest disadvantage of spin coating is its low coating efficiency. Since as much as 95% of the material is spun off the wafer during the coating process, waste as well as production costs must be considered. For example, the disposal cost of resist waste is about 0.45 euro per liter, so that the overall cost of using the spin-coating method is 160% that of the resist actually consumed.3

The volume of material consumed in a standard (1–2-Ám) spin process is 4 ml. However, to deposit resist layers thicker than 4 Ám or layers over high topography (as in MEMS applications), the volume of material required is even higher. Based on supplier production-line data, 3.5–5 ml of resist is required to coat a 100-mm wafer with a target thickness up to 10 Ám.

In general, the thickness of a spin-coated layer depends solely on the spinning speed and the viscosity of the resist. However, when high-viscosity material is used, the amount required is even higher to obtain a good coat. The spin-coating tests described here used thick AZ4562 resist from Clariant (now AZ Electronic Materials, Somerville, NJ), which has a solids content of 39.5%.

Spray Coating. The spray-coating tests for this study were performed on a 101 system from EV Group (Schärding, Austria). The tool's atomizer nozzle is designed to produce micron-sized droplets of resist. During the spray process, the wafer is rotated at a low, angular velocity while the spray nozzle moves across the wafer surface. Dispense volume can be selected to achieve different film thicknesses. The spray-coating method has more process variables to influence the resist thickness than the spin-coating method. The thickness of the resist layer deposited using the EVG 101 system is determined using the following formula:4

where d = resist thickness (Ám), c = the solids content of the resist solution (%), k = the distance of one scan segment (steps), CE = coating efficiency (%), S = wafer area (cm2), Vdis = volume dispensed (Ál/sec), and vn = the scanning speed of the spray head in segment n (steps/sec) (n = 1, 2,...,15). The value 10–3 comes from the unit converter.

This formula can also be used to calculate coating costs by determining the volume of resist consumed. In that case, the resist thickness achieved through spray coating is derived from the following equation:

where d is the film thickness, V is the volume of resist on the wafer, and S is the wafer area.

The main factors affecting CE are the size and geometry of the substrate, equipment maintenance needs, and the specific spray method and tool configuration, such as atomizing air pressure, spray head, etc. In general, the CE of a specific coating tool can be determined by practical data or provided by the equipment supplier. Thus, the volume of resist on the wafer is calculated as follows:

V = Vtt  X c  X CE

where Vtt is the actual total volume of material consumed (in contrast to the volume of resist deposited on the wafer).

When the first and second equations are combined, the total volume of resist consumed (Vtt) can be expressed as follows:

Vtt = Vdis X ttsc

where Vdis is the dispensed volume of resist (Ál/sec), which can be controlled by the resist pump and the software, and tsc is the total scanning time of the spray head, which sweeps from one side of the wafer to the other. The scanning time is determined by the scanning speed of the spray head.

In the experiment presented here, the scanning time was fixed at 60 seconds for a specific coating recipe. Practical data showed that the spray tool's CE was about 20%. The wafer area on a 100-mm wafer is 78.5 cm2. When the second, third, and fourth equations are combined, the consumed resist can be calculated as followed:

This equation is used to determine the volume of resist consumed for known target film thicknesses. Using it, the investigators were able to calculate the number of wafers that were coated and the cost of resist at different film thicknesses. In Figure 2, the relation between the volume of resist consumed and the resist thickness is plotted for solutions with solids contents ranging from 5 to 15%. In fact, CE is only an approximation value. Operator skill and tool maintenance are very important for achieving stable CE values.

Figure 2: Volume of photoresist consumed versus resist film thickness.

Although the spray coater in this experiment can use only low-viscosity solutions (<20 cSt) or those with low solids content, thick resist layers can be formed using solutions with a low solids content. By using solutions with a low solids content, device manufacturers can reduce resist costs because solids are the expensive part of the solution.

The experiments reported in this article compared two types of resist. The first, AZ 4823, is a commercial spray-coating material with a solids content of 15%. The second, a version of AZ4562 diluted in methylethyl ketone (MEK), is used to coat high-topography wafers and has a solids content of 10%. The solids content in 1 L of diluted AZ4562 solution is 75% less than that in 1 L of regular AZ4562.

Figure 3 shows the number of wafers coated per liter of resist using a spin coater with AZ4562 and a spray coater with either AZ4823 or dilute AZ4562. The volume of resist used for each wafer in the spin-coating process was 3 ml to achieve a target thickness of 3 Ám and 4–4.5 ml to achieve a thicker layer. The resist volume used in the spray coater was determined using the fifth equation. While AZ4823 in the spray system coated the largest number of wafers per liter, AZ4562 in the spin system coated the lowest. (The former was 2–3 times larger than the latter.)

Figure 3: Number of wafers coated using 1 L of photoresist on spin and spray systems.

The cost of resist used to achieve different film thicknesses is plotted in Figure 4. Spin coating is the most expensive process, while spray coating using AZ4562-MEK is the lowest.

Electrodeposition Coating. The ED coating process is quite similar to electroplating. It uses a resist solution in the form of an emulsion with a solids content of 10%. The solids particles, which are approximately 100 nm in size, are positively charged for positive resist and negatively charged for negative resist.

Figure 4: Cost of photoresist per wafer using spin-coating and spray-coating systems.

ED coating requires a conducting seed layer on the wafer surface. When high voltage is applied between the conducting layer and the counterelectrode, the resist particles migrate and deposit on the seed layer to form a resist film. The deposition step occurs within a few seconds. Since the resist is an insulating layer, the current decreases rapidly as the resist thickness increases. Deposition stops when the current drops to zero.

Although ED has a higher CE value than either the spin or the spray method, it is performed in a bath. Therefore, its cost depends on the lifetime of the resist bath and the throughput of the coating process.

Figure 5: Cost per wafer versus lifetime of photoresist bath using an electrodeposition coating system.

To evaluate the cost of the ED coating process, resist bath, wafer throughput, and coating frequency data were considered in the laboratory. These data were collected for three baths that used Eagle 2100 negative resist from Shipley (now Rohm and Haas Electronic Materials, Marlborough, MA). Coating was performed on a Resist Coater ED plating system from Meco (now Besi Plating, Drunen, The Netherlands). While it is difficult to pinpoint the cost of the resist used in this test because of its fluctuating market price, a calculation was made for coating 100-mm wafers with a target thickness of 10 Ám. Figure 5 shows the relationship between cost per wafer and bath lifetime. The curve is based on the data summarized in Table I. The per-wafer cost of resist drops rapidly as bath lifetime increases. For example, cost per wafer for a one-year bath lifetime is one-tenth that for a one-month lifetime. In addition to achieving long bath lifetimes, the ED coating system's high capacity helps reduce the cost of resist.

Test Parameters
Bath A
Bath B
Bath C
Photoresist price (euro/liter)
300
150
150
Throughput (wafers/day)
25
25
10
Coating Days (days/month)
22
22
10
Wafer diameter (mm)
100
100
100
Coating thickness (µm)
10
10
10
Table I: Electrodeposition resist-coating bath data.

Conclusion

Spin, spray, and electrodeposition methods have been investigated to determine resist consumption levels and costs. The volume of resist consumed in a spin coater is higher than that consumed in a spray coater, resulting in higher cost per wafer. The volume of resist used in spray coating can be controlled by several parameters, such as layer thickness and the solids content of the resist solution. The cost of resist used in the ED method is strongly dependent on the lifetime of the resist bath and the throughput.

The identification of the parameters that affect the volume of material required to coat wafers or resist costs per wafer is very useful for estimating total costs. Furthermore, it can help manufacturers choose solutions that reduce resist consumption or perform process optimizations. Reducing resist consumption and fluids waste is crucial for achieving low-cost manufacturing goals.

Acknowledgments

The authors wish to acknowledge the whole IC-process group of DIMES-Delft University of Technology for its technical support.

References

1. NP Pham et al., "Photoresist Coating Methods for the Integration of Novel 3-D RF Microstructures," IEEE Journal of MEMS 13, no. 3 (2004): 491–499.

2. C Christensen et al., "Wafer Through-Hole Interconnections with High Vertical Wiring Densities," IEEE Transactions on Components, Packaging and Manufacturing A 19, no. 4 (1996): 516–521.

3. P Haaland, J McKibben, and M. Paradi, "Fundamental Constraints on Thin Film Coatings for Flat Panel Display Manufacturing," in Proceedings of the Display Manufacturing Technology Conference (San Jose: SID, 1995), 79–81.

4. NP Pham, JN Burghartz, and PM Sarro, "A Model for Film Thickness Using Direct Spray Coating," in Proceedings of the IEEE Electronics Packaging Technology Conference (Piscataway, NJ), 773–776.


Nga Phuong Pham, PhD, performs postdoctoral work at Delft University of Technology (The Netherlands). Her research interests include micromachining technology for radio-frequency and IC components, lithography for special applications, and 3-D integration. From 1997 to 1998,  she worked as a research assistant in the surface and intersurface of advanced materials group at the Centre Commisariat d'Atomique (Saclay-France). She received a PhD in electrical engineering from Delft University of Technology. (Pham can be reached at +31 15 2781237 or nga@dimes.tudelft.nl.)

Pasqualina M. Sarro, PhD, is responsible for research on integrated silicon sensors and microsystems technology at Delft University's Institute of Microelectronics and Submicron Technology (DIMES). From 1981 to 1983, she was a postdoctoral fellow in the photovoltaic research group in the engineering department at Brown University (Providence, RI). In 1996, she became associate professor in the electronic components, materials, and technology laboratory at Delft University, and, in 2001, she become A. van Leeuwenhoek professor there. The author and coauthor of more than 250 journal and conference papers, she reviews for several journals. She received a laurea (MS) degree in solid-state physics from the University of Naples, Italy, and a PhD in electrical engineering from Delft University in the area of infrared sensors based on integrated silicon thermopiles. (Sarro can be reached at +31 15 2787708 or sarro@dimes.tudelft.nl.)

Jurgen Bertens is a wafer technology engineer at Besi Plating  (Drunen, The Netherlands) and is actively involved in ED resist coater development. Since 1997, he has worked at DIMES as process engineer on the location-controlled crystallization of silicon with an excimer laser. He received a BS in applied physics from HTS Eindhoven, The Netherlands. (Bertens can be reached at +31 416 384384 or jurgen.bertens@besiplating.com).

Lucas van den Brekel, PhD, is responsible for operational support and process development for the production and implementation of electroplating equipment at Besi. He joined Meco Equipment Engineers as a process technology manager in 1996. Before that, he worked at Unilever Research & Development in the area of detergents processing. He received a PhD in chemical engineering from the Technical University of Delft in 1987. (Lucas van den Brekel can be reached at +31 416 384384 or lucas.vandenbrekel@meco.nl.)


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