The choice to locate this year's European Advanced Equipment Control/Advanced Process Control Conference in Dublin had a certain logic to it. After all, two global companies with a mighty presence in the area around the Irish capital—Guinness and Intel—know a thing or two about how to tightly control their processes. Anyone who's ever quaffed a perfect pint of the black stuff has experienced the brewer's chemical processing expertise, while untold hours of failure-free digital heavy lifting pay silent homage to the microprocessor megacorporation's manufacturing prowess and product reliability.
Guinness's process control methods may be more mature than those of Intel and the rest of the semiconductor community, yet many papers at this year's European AEC/APC event presented more real-world, data-driven results than in years past. For example, fault detection and classification (FDC) and run-to-run control schemes have become increasingly reliable and are now deployed at Intel, AMD, and other leading-edge fabs. Although outstanding progress has been made over the past few years, many obstacles remain on the path to 100% automated, totally controlled, fault-free chipmaking.
During his welcome address, Jim O'Hara, an Intel vp in the technology and manufacturing group and gm of the company's Irish operations, said that Intel's local fabs are driving to have 100% FDC capability throughout the entire suite of fab tools by the end of this year. (The figure stood at 80% when he gave his speech in April.) After mentioning benefits seen in production yields, quality, and process technology performance, he cited one specific example of a 10–20% improvement in etch tool fault detection and resolution.
More evidence of Intel's efforts came during Ravi Khairate's presentation on the strategy and results of pervasive FDC use in the company's high-volume 300-mm, 90-nm technology fabs. He detailed such benefits as minimized wafer loss during excursions, reduced maintenance costs, detection of equipment variations, and increased tool availability. Among his case studies was one involving ashers, where FDC data helped identify failing temperature profiles and the root cause, a faulty thermocouple. As a result of this diagnosis, Intel worked with the thermocouple supplier to redesign the component and eliminate the failure mode, leading to a 7% uptick in tool availability.
Tom Sonderman, AMD's point man for the company's automated precision manufacturing efforts, updated the Intel archrival's pursuit of full, true factory automation and control. One key, he said, is the integration of production scheduling and APC. With first silicon having started the previous week at AMD's inaugural 300-mm fab, Fab 36 in Dresden, Sonderman's comments were unusually timely. During his speech, he discussed what turned out to be one of the key challenges repeated over the course of the conference: How to deal with "exception handling," both in terms of writing the phenomena into the software and how to overcome it in production. Sonderman noted that exception handling must be automated in order to fully integrate manufacturing, pointing out the major impact that "process control business logic" can have on tool idle time and utilization.
Although personnel issues didn't get much attention at the conference, the topic looms as potentially troublesome. One engineer from a major IC manufacturer expressed his concerns in an e-mail sent after the show: "Where are the next groups of FDC and APC engineers going to come from? There is a well-established tradition for APC in the chemical engineering community, but the idiosyncracies of semiconductors do not seem to be well handled in schools. As for FDC—especially the classification part—there are very few programs zeroing in on this area, let alone handling it from a semiconductor perspective."
He's right. It won't help for the toolsets, subsystems, and software to be able to attain total factory- and enterprisewide AEC/APC if there aren't enough well-trained, qualified people to make the whole thing work together.