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BEOL Processing:

Surface prep, cleaning, stripping of low-k dielectrics, copper interconnects become more problematic

Whether it's in the front end or the back end of the process line, the cleaning, stripping, and other preparation of the wafer surface becomes ever-more challenging as geometries shrink to 65 and 45 nm and beyond. One central question facing both ends of the line is how far existing surface conditioning techniques and chemistries—both wet and dry—can be extended. And when the time comes to make the jump and bring in new toolsets and processes into the fabs, which of the emerging surface technologies looks the most production worthy and economical, and at what node will it need to be introduced?

In the realm of low-k dielectric materials, already fragile film structures are increasingly susceptible to damage as the k-value decreases, potentially exacerbating defectivity and adversely affecting yields and reliability. This is especially true with the advent of porous low k, since porosity introduces a host of process integration and materials compatibility difficulties. The balancing act between maintaining the film's integrity and integrating it properly and performing the necessary stripping, cleaning, and conditioning gets increasingly precarious. Other issues include how and when to characterize the materials, how to keep interline capacitance and interconnect resistance to a minimum, and limiting yield- and reliability-degrading factors such as electromigration, copper diffusion, stress voiding, and the like.

This issue's Hot Button experts from the chipmaking, research, and OEM communities address these and other critical topics, as they share their considered opinions about the challenges the industry faces in the area of BEOL surface technologies.

DIDIER LOUIS (back-end deputy manager and patterning manager, LETI): The 2004 update of the International Technology Roadmap for Semiconductors calls for the use of low-k dielectric materials (keff< 2.6) at the 45-nm node. To address that, the incorporation of free volume or porosity as well as a high carbon rate in the dielectric are commonly used to lower a material's dielectric constant. Unfortunately, the mechanical properties of porous low-k degrade rapidly as the k-bulk value is reduced, which is cause for concern at the CMP and packaging steps. Patterning processes (etching, stripping, and cleaning) can also have a drastic impact on the integrity of the porous low-k.

Ashing plasma and wet chemical exposure are enhanced by an increased porosity rate.
—Didier Louis

Dry etching on low-k materials can induce carbon depletion and film densification at the same time by creating an SiOx-like film. Indeed, fluorine gas reacts with the carbon content on the low-k material, depletes it, and creates a densification of the film. This phenomenon becomes more and more important as the porosity rate increases. The challenge consists of how to adapt the right C/F ratio, by taking into account the nature of the etched material and more particularly its carbon content.

With photoresist strip, ashing plasma and wet chemical exposure may cause surface and bulk low-k carbon depletion and make the dielectric prone to absorb moisture or residues from the stripping processes. These two phenomena are, like etching, enhanced by an increased porosity rate. For dry ash, the reduction of ash chemistries causes less damage than oxidation. In the downstream mode, a high temperature is needed to reach critical efficiency levels. Adapted chemistry could saturate the dielectric carbon link and minimize its impact (i.e., NH3). The general tendency is to minimize the material modification by using either a reducing chemistry (e.g., He-H2, N2-H2, NH3) or oxidizing chemistries in reactive ion etch mode in a very low pressure range (< 20 mTorr).

Another approach is to use the material modification induced by the dry plasma to facilitate integration steps. The ash plasma can protect the low-k material by using a polymerizing chemistry (C4F8, CH4) with a low plasma dissociation rate. In this case, plasma plays two roles: the main role is to strip the resist, while the secondary one is to deposit material in situ on the feature sidewalls. The pore-sealing effect is then obtained. A C/F CVD technique might also seal the pores.

For wet cleaning and surface conditioning, dilute HF is still used everywhere and is relatively cheap. The problem with porous low-k material and porous damaged material is the compatibility. New, more-compatible, and efficient chemistries are emerging. Very diluted organic acids mixed with adapted surfactants have shown good results, although water and surfactant absorption into the pores remains an issue.

New emerging technologies such as ion flux, cryogenic, and supercritical fluids are under investigation. Supercritical carbon dioxide efficiently removes contaminants trapped in the pores and facilitates the sealing or repair of organic molecules (HMDS or equivalent), but it does not solve the effectiveness/compatibility dilemma. However, the new cryogenic surface-conditioning approaches might offer a solution.

Characterization is also very challenging. What is the right characterization technique and at what step do we use it? To characterize porous material evolution after the patterning process and to predict in advance any potential k-value shift, new in-line and off-line techniques can be used, such as ellipsometry porosimetry, x-ray reflectometry, x-ray fluorescence, and x-ray photoelectron spectroscopy. However, resistance-capacitance measurements, though they are expensive and time consuming, remain the most accurate technique to evaluate the impact of process integration steps.

JEFF WEST (BEOL process integration manager, Texas Instruments): With each migration to a lower-k dielectric, surface preparation requirements become increasingly restrictive. Low-k films are more susceptible to etch and ash damage and as a result can exhibit accelerated lateral wet-strip removal rates. For 90-nm processes and beyond, such films are often embedded below more-robust higher-k hard masks that can withstand plasma damage. In such cases, it is critical that the dry and wet clean processes minimize the extent of retrograde via and trench profiles that otherwise could lead to void formation during subsequent metallization. The ability to detect such voids is limited: Short of an in-line optical beam-induced resistance change (OBIRCH) technique, subsurface voids may not show up until final probe or later.

Interface engineering has emerged as a critical activity for ensuring the reliability of copper interconnect systems.
—Jeff West

Additionally, traditional wet cleans that incorporate high-cleaning-efficiency ultrasonic or megasonic chemical agitation can physically crack or rupture the fragile, freestanding, high-aspect-ratio dielectric "walls" temporarily created during damascene fabrication schemes. Reducing the aggressiveness of the bath agitation generally requires extending the immersion time to compensate for the reduced cleaning efficiency, but this can lead to the kind of retrograde profiles mentioned above. This catch-22 situation has driven many to abandon traditional bath-immersion techniques in favor of single-wafer spin-processing solutions that rapidly flush released defects from the wafer surface.

One less-appreciated challenge to 300-mm wafer processing is the inevitable increase in mechanical damage at the wafer bevel which results from point contact between a higher-mass wafer and carriers/handlers throughout the manufacturing line. There is ample opportunity for defectivity generated by crushing dielectric films at the wafer edge, particularly for some of the more-complex interconnect schemes embedding eight or more metal/low-k levels. If not properly addressed, this defectivity source will ultimately degrade yield or reliability. This becomes even more critical as active die are placed as close as possible to the edge to maximize salable real estate and lower the manufacturing cost per die at 300 mm.

Finally, "interface engineering" has emerged as a critical activity for ensuring the reliability of copper interconnect systems incorporating low-k films, with film adhesion and electrical breakdown strength requiring careful cooptimization to achieve robust product life. A case in point is for organosilicate glass (OSG), where the usual NH3 pretreatments done to reduce slight surface oxidation of the embedded copper leads can degrade the interface strength between OSG and the subsequently deposited dielectric barrier.

IVAN "SKIP" BERRY (director of technology and strategic marketing, Axcelis): When you consider the breadth and depth of BEOL manufacturing challenges, it's not hard to see why the introduction of a new material into semiconductor processing is such a rare event. The integration of new low-k dielectrics and copper, for example, continue to present many technical challenges, and just when you get close to solving one challenge, another two emerge.

Cleaning and surface preparation will play a significant role in enabling ALD films.
—Skip Berry

BEOL technical issues can be grouped into three major categories: achieving low interline capacitance, attaining low interconnect resistance, and enhancing yield and reliability. In each area, surface conditioning and cleaning processes will play an important role in helping overcome these challenges.

Because there is no dielectric material that offers all of the necessary properties to enable reduced interline capacitance, other materials are added to compensate for low-k dielectrics' weaknesses. However, etch stops, caps, diffusion barriers, and other added materials tend to increase the interline capacitance or the line resistance.

PVD metal diffusion barriers, when made thick, consume a significant percentage of the interconnect cross section and are difficult to process pinhole free when made thin. To achieve thin, pinhole-free barriers with smooth surfaces, the pores of the low-k material may need to be sealed. Many proposed pore-sealing approaches are a component of the cleaning process. The challenge is limiting the sealing to the first few monolayers, otherwise an unacceptably high capacitance may result. Current processes tend to create relatively thick damage regions. Filling the surface pores with a large organic molecule, one that is large enough to prevent penetration into the bulk dielectric, may be a solution to pore sealing, but much work still needs to be done to achieve this and understand its impact on reliability and adhesion.

As copper linewidths shrink, the resistivity increases because of grain-boundary scattering—since copper grain growth is being constrained by the needed narrow, high-aspect-ratio line used in damascene processes—and increased surface scattering, which becomes a more significant component of the resistance. While large grain growth with low resistivity can be achieved in the copper overburden and other thin films, these large grains fail to grow into trenches and vias. Engineering the copper to the barrier/plating base to enhance grain growth has attained limited success. Atomic layer deposition (ALD) may enable large grain growth and generate smoother surfaces, reducing both grain boundary and surface scattering, but results so far are limited, and these techniques generally make adhesion worse.

Cleaning and surface preparation will play a significant role in enabling these ALD films, since proper surface terminations (Si-OH bonds, for example) may be required to get good nucleation and adhesion. If Si-OH termination is required, it must be limited to within the first monolayer. Si-OH bonds within the bulk will raise the dielectric constant and be potential nucleation sites for the deposited barrier layers. The aforementioned pore-sealing technique may restrict the Si-OH termination to the near surface, but it is unclear whether it will impede uniform barrier nucleation.

The majority of BEOL challenges fall into the yield and reliability category and can be the most difficult to diagnose and solve. These issues include electromigration, stress voiding, copper diffusion, water absorption, cracking, peeling, dielectric breakdown, and defectivity. Low-k dielectrics tend to be mechanically and electrically weak, hydrophobic, and porous and are a significant cause of many reliability challenges. These hydrophobic materials are difficult to clean, have poor adhesion, and when made porous, act as efficient hydrocarbon sponges. Surfactants are being explored to improve wet cleaning efficiency by reducing the contact angle, but rinsing (the removal of the surfactant) and drying can be problematic. Surfactants and any organic components of semiaqueous cleaning chemistries must be carefully used so that they are not absorbed into these hydrocarbon sponges.

BRIAN FRASER (single-wafer product marketing manager, Akrion) and ISMAIL KASHKOUSH (manager, process development and process support, Akrion): Traditionally, BEOL postetch/ash cleans have been performed in a spray tool or wet bench with a commercially available solvent. Removal of the residue from the etch and ash processes has been accomplished primarily by chemical dissolution. Physical cleaning methods such as megasonics have not been used because of equipment limitations and also because of damage to sensitive structures.

Although the chemical process removes much of the residue, there is some remaining nonsoluble contamination. Recently, these particle defects have had considerable impact on device yield, for both aluminum and copper metallization. Single-wafer spray tools have shown some improvement versus the traditional batch tools, but adequate removal of these defects requires some physical cleaning method.

Attempts to address this issue have included processing the wafers through a jet-style megasonic tool after the spray-tool clean. However, the jet-style megasonics have reached their technical limitation, since this method causes damage to sensitive structures (though there is ongoing work with new versions). Cryokinetic tools—which use argon and nitrogen crystals to remove particles by momentum transfer—have also been employed after the spray tool.

The aforementioned methods require a separate tool for the residue- and particle-removal steps. Some single-wafer tools combine residue removal by chemical methods and particle removal by physical methods in the same chamber. Controlled single-wafer megasonics have been shown not to damage sensitive structures such as aluminum lines and the dielectric material between trenches. The use of megasonics greatly decreases the level of defectivity and also permits shorter process times.

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