design to yield
production chips in 2005
is no longer an unknown quantity for backers of a collaborative effort
to develop a workable interconnect chipmaking process with diagonal routing.
Participants in the X Initiative endeavor have spent the past four years
trying to answer the manufacturing, cost, and yield questions about the
technology, which uses strategic diagonal interconnect routing as its
X: An example of X architecture layout (left) alongside a real-world
Toshiba digital TV chip using the diagonal design, a device Toshiba
says was 11% fatser, with less logic area, than a comparable IC.
SOURCE: X INITIATIVE
2005, they insist, is the year that the responses will free the concept
from its test phase to deliver actual product. In 2004 Toshiba, an initiative
cosponsor, used the technology on the fourth- and fifth-metal layers to
produce a 180-MHz chip at the 130-nm process node. Designed for digital
television, that device was 11% faster and had a 10% smaller logic area
than a comparable IC. In a major announcement on April 11, UMC said it
is the first pure-play foundry to qualify design rules for chips based
on X architecture at the 90-nm process node. The Taiwan-based foundry
is prepared to process IC designs using the architecture.
architecture bypasses the semiconductor industry's traditional search
for improvements in processes and materials to focus on metal layers four
and five of multilevel chip architecture.
X design retains the common Manhattan-style 90° angles on layers one
through three. Although it's not a new concept, the technology always
lacked the proper industry infrastructure until Simplex Solutions, a software
and design service company that is now part of Cadence Design Systems
(San Jose), teamed with Toshiba four years ago to start the ball rolling.
the interconnects at a 45° angle on the two uppermost metal layers
reduces device wiring by more than 20% because wires can be sent in eight
different directions. Device performance shows increases of more than
10%, proponents of the technology say. In addition, the diagonal routing
produces 30% fewer vias and 30% more semiconductors per wafer for system-on-chip
process and timing yield will show improvements, according to supporters.
A study conducted in mid-2004 by PDF Solutions, an early initiative supporter,
used yield prediction software to determine all the critical areas for
opens and shorts in X architecture. A second finding determined that overall
hot spots and the intensity of hot spots also decreased.
information comes from the X Initiative, a consortium of more than 40
companies that was launched in 2001. Most observers intuitively understand
that diagonal wiring "makes sense," insists Ketan Joshi, director of marketing
for the initiative. But the technique has always raised questions. "Why
aren't people doing this? Is there something wrong with it. Can you actually
Design Systems and Toshiba cosponsored the X Initiative, which set out
to establish a "design chain" in order to prove the worthiness
of the technology to the engineering community "in a
more rigorous fashion," notes Joshi. When Aki Fujimura, X Initiative
steering group member and CTO, new business incubation at Cadence, began
laying the initiative's groundwork, "he visited each piece of the
supply chain—for example, maskmakers, wafer exposure tools, and
so on. Every person told Aki, 'I don't see any issues in my area. I can
make it work, but I don't think others can.' At the end of the day we
pretty much realized we can do this if all the pieces of the supply chain
the collaboration started under the X Initiative umbrella brought a dawning
realization to each disparate link in the supply chain. Participants discovered
that they had the wrong perceptions about whether diagonal routing's technical
issues were surmountable, Joshi says.
2003 the consortium confirmed first-silicon design rules. Joshi notes
that member companies such as Applied Materials, STMicroelectronics, Infineon,
UMC, and TSMC "all have consistently shown that test chips, in terms of
design rules, are quite comparable to Manhattan. Obviously, the next step
is complete design and production."
a skeptical Toshiba kept its options open during development of the 130-nm
production chip. "They wanted to have an option," Joshi says, "so they
ran a shadow project. They had two teams, one on X and one on Manhattan."
Toshiba's goal was to design a 162-MHz chip, but a couple of months into
the project the manufacturer "reached 180 MHz with X. At that time they
were so confident, they canceled the Manhattan project."
2003, Patrick Lin, chief SOC architect at UMC, says it was difficult for
the foundry to assess the level of customer interest. In particular, the
management needed to determine "from the design side whether the charter
of the X
Initiative would be accepted by the public or not."
UMC confirmed customer interest in diagonal routing, the foundry turned
its focus to technological matters. "We had to make sure that the architecture
was compatible with our existing process," Lin explains. Specifically,
UMC wanted to ensure that it would need to make only minor process modifications
and then qualify the process. "We had to design the test structure to
make sure that the design rules meet our quality standards. So that's
where we spent most of our time and effort."
design rules target their X architecture designs to UMC's process technologies,
Lin points out. UMC did modify specific design rules, particularly "the
via that goes outside the metal line. We wanted to see if it always does
that or not because of its 45° nature."
the manufacturing side, he says that a test chip put through stress testing
at 225°C revealed "very little degradation in the resistance
shift." In addition, UMC wanted to ensure that electrical migration
reliability was not a concern. The test chip results enabled the foundry
to verify "that our process is quite suitable for the X architecture."
says that UMC has heard from potential customers interested in the X-architecture
devices. "We began receiving requests before our 130-nm process became
available. They keep on migrating to smaller and smaller geometries, and
that's why we set out to do this qualification task." Most of the interest
has come from customers in the United States and Japan.
whether the diagonal routing will cause an increase in photomask costs,
Lin replies, "As far as I know, there is no extra cost whatsoever.
But in preparing the mask itself we've taken care of the OPC (optical
proximity correction) issues when we're doing the 45° [routing]. We
don't see any problem doing that."
he insists, "should be comparable with yields of lines routed with the
Manhattan architecture. We hope that fabless semiconductor companies will
realize the advantage of this X architecture and start taking advantage
of it." Given UMC's broad customer base, Lin predicted that the first
type of customers to announce that they are taking advantage of the X
architecture will be those that design digital consumer electronics products.
the X Initiative was launched in 2001, early participants raised concerns
that the photomask realm could face challenges unique to X architecture.
A chief worry was that mask-writing tools—and vector scan tools
in particular—may need longer operating times than raster scanning
machines. After four years of work, most of the concerns have been addressed,
according to a
member of the initiative's steering committee.
Jordan, the Toppan Photomasks representative with the steering group,
says that the work with the mask-writing tools has shown encouraging
results. In X-mask tests, the company has been working with laser writing
tools that use a raster-scan technique. The results have shown equivalent
had no negative write times compared with Manhattan geometries," Jordan
explains. He adds that a couple of test runs on vector scan systems by
other X Initiative members also have shown equivalent write times. "In
theory, there's some impact with vector tools when you get into an angled
geometry. Overall, though, the impact of Manhattan to X has not really
steering committee member asserts that the consortium has made the case
that X is production ready. "At this point we've pretty much demonstrated
manufacturability of 65 nm. In fact, we demonstrated manufacturability
through 65 nm, and that really refers to all aspects of maskmaking, whether
it's data preparation, writing, inspection, defect inspection and repair,
or metrology and design rules. The ability to hit specs has been demonstrated
as equivalent also."
emphasizes that throughputs using advanced masks in the X-architecture
tests were three times better
than normal. Testing has shown that the costs associated with photomask
use have been comparable with non-X processes. "We've found that the production
flow and processes for masks, including the major costs for write time
and inspection, are equivalent."
participating members did have doubts that were dispelled as the X project
progressed. Mike Smayling, the CTO of Applied Materials' Maydan Technology
Center, admits that there "were always concerns at each step in the design
chain. Will the layout tools work properly? Will the verification tools
Materials produced the industry's first 65-nm interconnect test chip using
X architecture at the Maydan facility in Sunnyvale, CA, in early 2004.
Cadence provided the design and validation tools, while Canon provided
its ArF lithography system. The device featured multilayer copper/low-k
interconnects on 300-mm wafers. Applied used its wafer inspection and
metrology tools to measure critical dimensions and defects. It helped
that Applied's Etec unit had been involved with the consortium "from a
mask-writing standpoint" from the beginning, Smayling notes.
thought there would be a low risk at each step," he says. "We thought
the tools were in good shape, since we had already tried a design flow
at 90 nm, and it worked. So we were fairly confident that our methodology
should continue to work, and that fortunately was the case."
there was a concern about the diagonal routing's impact on process tools.
"Certainly, we had some concerns with things like CD-SEMs, the inspection
tools and also some of the other tools like our etchers and our CMP systems,
which have in situ monitors that could be fooled by some pattern. We wanted
to confirm that they would in
fact work fine and not be fooled by diagonal wiring."
and others at the technology center were concerned in particular about
inspection tools or in situ monitors set up for Manhattan-style features.
"Diffraction patterns or interference patterns coming off of a standard
layout would be oriented in a very predictable way, and if you had a detector
and sensor set up only for that style of layout, you would completely
miss signals coming off of X patterns. It proved not to be the case, due
to the system designs with multiple detectors. The inspection tool did
not have any particular spatial resonance because of diagonal routing."
For metrology, Applied's CD-SEM tools have the software "to allow
measuring critical dimensions at 45° [angles].
an EDA standpoint, Smayling believes specialized tools exist now that
"more efficiently handle X-type layouts." He and his colleagues were heartened
to see that OPC tools were able to handle diagonal layout correctly, although
some had to be fixed.
ran across a bug in one of the tools that ended up putting one of the
edges on a Manhattan layout instead of a diagonal one. That was fairly
quickly resolved by the tool vendor."
sorts of solutions appear to be a prominent feature of the X Initiative
endeavor. Some members say the consortium is a good example of industry
cooperation, where various supply-chain partners work together to figure
out all the angles, so to speak.
good news, and any time you see a steady stream of good news it's usually
because of some malice aforethought," Toppan's Jordan muses wryly.
"There are always little problems along the way, and fortunately
with X we were able to get far enough ahead of the design introduction
to really smooth the path quite a bit."
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