gate stacks using high-kfilms are being introduced into
production to address device-scaling requirements.1
The state of the silicon surface before the deposition of high-k materials
such as HfO2
and HfSiO is extremely critical to the performance of these gate dielectrics.2
Therefore, the formation of a stable and consistent Si/high-k interfacial
layer is essential for ensuring device properties such as carrier
mobility. This layer is also necessary to achieve a consistent and
linear high-k dielectric deposition rate.1–3
Silicon nitride, silicon oxynitride, and thermally and chemically
grown silicon oxide interfacial layers have been investigated by many
research groups. Of all the films studied, silicon oxide is the most
promising candidate because of its long history in the industry.
methods have been proposed to form interfacial silicon oxide layers
on silicon surfaces: thermal oxidation and wet chemical growth using
ozonated DI water (DIWO3).
The main advantage of thermal oxidation is its consistent stoichiometry.
The drawback is that the extra thermal process step adds to the thermal
budget and causes dopant diffusion. In contrast, wet chemical oxidation
does not require additional process steps, since chemical oxide growth
can be performed as part of the pre-deposition surface-preparation
sequence in a single-wafer wet process tool.
these reasons, the use of chemical methods to grow oxide interfacial
layers has been a very active research topic.1–3
Although these investigations have provided insights into the impact
of the interfacial layer on the performance of the gate stack, they
have not yet led to a viable production process.
article discusses the results of a chemical process for growing an
oxide interfacial layer using ozonated DI water. Based on tests performed
by SCP Global Technologies (Boise, ID) at customer sites, the article
investigates the role of oxide thickness and nonuniformity as a function
of the dissolved-ozone concentration and contact time. It also demonstrates
that the use of a controlled etchback step on an as-grown oxide surface
achieves a precise film thickness.
the experiments highlighted here were performed on an Emersion single-wafer
process tool with a 200-mm chamber from SCP Global Technologies. A
Liquozon 100 ozonated-water delivery system from MKS Instruments (Wilmington,
MA) was used to provide the required DIWO3
the oxide-growth tests, p-type bare silicon wafers were first processed
in 100:1 hydrofluoric acid at 22°C for 30 seconds to strip the
native oxide layer. Then ozonated DI water was introduced into the
process chamber to chemically grow a thin oxide layer. In all tests,
the ozonated DI-water flow rate was 20 L/min. The concentration of
dissolved ozone was measured in the ozonated-water delivery system
using an ultraviolet-based dissolved-ozone monitor. After the introduction
a 5-second rinse step was performed followed by a drying step using
SCP Global's Enhanced Marangoni drying process, which has been detailed
the controlled etchback tests, DIWO3
with an ozone concentration of 40 ppm was introduced into the tool
chamber to grow the thickest possible oxide layer on the wafer surface.
The wafers were then etched using 100:1, or in some cases 200:1, hydrofluoric
acid at 22°C to remove a few angstroms of the oxide film. Film
thickness was measured with a NanoSpec 9300 thin-film metrology tool
from Nanometrics (Milpitas, CA) using nine-point scanning. The same
tool was used to calculate film nonuniformity based on the raw data
and the following formula:
range = maximum film thickness – minimum film thickness.
wafers were processed using the same process steps described above.
The oxide-growth and etchback steps were performed in one sequence,
after which the high-k dielectric film was deposited within a one-hour
Tests Using DIWO3.
The thickness and nonuniformity of the as-grown oxide layer formed
using the DIWO3
method were investigated as a function of DIWO3
processing time and ozone concentration in DI water. The results of
these tests are presented in Figures 1 and 2. It can be seen in Figure
1 that the oxide thickness increased rapidly at the onset of processing
but saturated after 30 seconds for all concentrations, achieving a
thickness of approximately 8 Å. Even long process times with
a high dissolved-ozone concentration of 40 ppm did not produce a measurable
increase in film thickness, indicating that the thickness saturated
at approximately 8.5 Å. That saturated film thickness agrees
with the reported values from other researchers.3
|Figure 1: As-grown oxide film thickness
as a function of DIWO3 processing time at various dissolved-ozone
concentrations. The data show that thickness saturation occurs
at ~30 seconds, regardless of concentration.
2 illustrates the nonuniformity of as-grown oxide films as a function
processing time at various dissolved-ozone concentrations. For all
ozone concentrations, a film nonuniformity of <1% could be achieved
only after the film reached its saturation thickness. For film thicknesses
below saturation (<6 Å), worse film uniformities of 10–20%
were achieved. To explain this phenomenon, investigators speculate
that oxide growth begins at highly active areas on the wafer surface.
In other words, it is not accomplished atom layer by atom layer.5
Before the film reaches its saturation thickness, islands or patches
of thin oxide film are present on the wafer surface. As the islands
grow, the oxide film gradually covers the surface, at which time the
diffusion of oxidizing species into the silicon surface slows down
and eventually stops.
|Figure 2: Oxide film nonuniformity as
a function of DIWO3
processing time at various dissolved-ozone concentrations for
as-grown oxide films. While process times of >30 seconds result
in saturated films and improved nonuniformity, these thicker oxide
films reduce gate-stack capacitance and thereby degrade channel
Etchback of Grown Oxide Films. It is well known that a nonuniform
interfacial layer results in high-k film-deposition problems. However,
a thinner silicon oxide layer is always desirable for achieving high
equivalent oxide thickness in high-k gate stacks.3,6
One way to solve this dilemma and create high-performance high-k dielectrics
is to grow the oxide layer to the saturation thickness to produce
the densest, most uniform layer and then etch the film back to the
desired thickness value for high gate-stack capacitance.
single-wafer immersion tool used to perform the tests highlighted
in this article provides excellent oxide etch characteristics because
of its fluid-distribution manifold design and its ability to start
and stop the etch process in less than 1 second.7
In addition, to meet accurate etch targets, the tool uses an etch
control algorithm that enables it to achieve the precision etchback
of saturated oxide films with a nonuniformity value of <1%.7
With these features, the tool can form thin and uniform interfacial
oxide layers for high-k applications.
|Figure 3: Within-wafer range values for
oxide films after etchback showing a sub-angstrom-level range
across the wafer. These values correspond to nonuniformity values
of 1–5% for the thickness range of 6 to 3 Å, respectively.
from controlled etchback tests on films grown using the DIWO3
method are presented in Figure 3, which shows the within-wafer film
thickness range versus final oxide thickness after etchback. The thickness
range values for all etchback films are 0.2 to 0.4 Å, which
is close to the metrology tool's measurement error. Hence, the uniformity
of etchback films is significantly better than that of as-grown films.
For example, a 6-Å etchback film has a nonuniformity of 1.5%,
whereas a 6-Å as-grown film has a nonuniformity of 10%. The
etchback data presented in Figure 4 demonstrate that the accuracy
of the target film thickness after etchback, as determined by the
etch control algorithm, is ±0.4 Å.
|Figure 4: Target etch amount versus actual
etch amount obtained using the etch control algorithm for as-grown
films with etchback. The results show that the maximum error is
<0.4 Å over the desired range of 3–6 Å.
Characterization. Following the development of the DIWO3
process, NMOS and PMOS transistors were fabricated with a variety
of interfacial layers before high-k deposition. Channel mobility data
from these transistors, which covered a wide range of channel lengths,
are presented in Figure 5. The transistors formed using the DIWO3
oxide-growth/etchback process demonstrated better channel mobility
than transistors with interfacial layers that were formed using a
thermal approach, indicating that single-wafer wet immersion processing
is a viable method for forming thin, uniform interfacial layers.
|Figure 5: Channel mobility data for 80-nm
transistors using high-k gate stacks with various interfacial
layers before high-k film deposition. The data results show that
oxide/etchback interface is comparable to or better than traditional
thermal barrier layers.
article has demonstrated that uniform ultrathin interfacial layers
for high-k dielectric applications can be formed using a DIWO3
oxide-growth process followed by precision etchback of the oxide film.
The uniform and controlled etching capabilities of the single-wafer
wet immersion process discussed here were used to achieve the best
reported uniformity values for ultrathin oxide interfacial layers.
High-k gate stacks on a variety of transistor devices built with the
interfacial oxide layer showed better channel mobility than gate stacks
manufactured using other processes and materials.
The International Technology Roadmap for Semiconductors,
Front End Processes (San Jose: Semiconductor Industry Association,
2004); available from Internet: http://public.itrs.net.
B Onsia et al., "On the Application of Thin Ozone Based
Wet Chemical Oxide as an Interface for ALD High-k Deposition"
(paper presented at the 2004 UCPSS conference, Brussels, September
J Butterbaugh et al., "Uniform Ultrathin Oxide Growth
for High-k Preclean" (paper presented at the 2004 UCPSS conference,
Brussels, September 19–22, 2004).
J Rosato et al., "Single-Wafer Wet Immersion Processing
to Address Sub-65 nm Surface Preparation Challenges," Semiconductor
Manufacturing 5, no. 5 (2004): 70–78.
M Hirose et al., "Initial Oxidation of Chemically Cleaned
Silicon Surfaces," Solid State Technology 34, no. 12
M Frank et al., "High-k Gate Dielectrics on Silicon and
Ge: Impact of Surface Preparation" (paper presented at the 2004
UCPSS conference, Brussels, September 19–22, 2004).
Y Lu et al., "Predictive-Based Model Control for Critical
Oxide Etches for Sub-100 nm Processes in a Single Wafer Wet Processing
System," in Proceedings of the ECS Fall Meeting (Pennington,
NJ: Electrochemical Society, 2003), 49–57.
Lu, PhD, is a senior process development engineer in the
R&D department at SCP Global Technologies (Boise, ID). Before
joining the company, he worked at Lucent Technologies and MEMC. The
author of more than 20 publications, he received a PhD in metallurgical
engineering from the University of Utah (Salt Lake City) in 1998.
(Lu can be reached at 208/685-3277 or email@example.com.)
J. Rosato, PhD, is a senior process development engineer
and executive member of the technical staff at SCP Global Technologies.
With more than 20 years of experience in the semiconductor industry,
he has contributed more than 50 publications to peer-reviewed journals
and proceedings. He received a BS in 1978 in chemical engineering
from Tufts University (Medford, MA), after which he received an MS
in 1985 and a PhD in 1987 in electrical engineering from the University
of Connecticut in Storrs. (Rosato can be reached at 208/685-3236 or
Baiya is a process development engineer at SCP Global Technologies.
His research focuses on the effect of wafer cleans on semiconductor
device performance. (Baiya can be reached at 208/685-4066 or firstname.lastname@example.org.)
Rao Yalamanchili, PhD, is director of the process R&D
group at SCP Global Technologies. He has authored more than 50 publications
in peer-reviewed journals and proceedings in the areas of particle
interactions and surface contamination. He received a PhD in metallurgical
engineering from the University of Utah in Salt Lake City. (Yalamanchili
can be reached at 208/685-4053 or email@example.com).