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DFM, nano partnerships form

SEMI has partnered with organizations on the design for manufacturing (DFM) and nanotechnology fronts. To address DFM issues, the Silicon Integration Initiative (Si2) and the equipment and materials trade association plan to collaborate on a number of near-term and ongoing efforts. Si2 will sponsor technical presentations and coordinate its member participation in the new EDA special exhibit area in the Emerging Technologies Hall at Semicon West, while SEMI will participate with Si2 in the Design Automation Conference and other upcoming EDA events. SEMI will also host a DFM workshop at its San Jose headquarters in fall 2005.

"The intrinsic problems facing ever-decreasing subwavelength ICs have created an economic imperative for the semiconductor industry to shift to the 'system view,' because isolated flows for design and manufacturing are growing more inefficient," said Steve Schulz, Si2's president and CEO. "Our member companies recognize this as an industry problem that can only be solved through broad cross-industry collaboration, especially with the types of companies represented by SEMI. We need to develop new standard interfaces, models, and semantics that permit streamlined data integration, opening up new opportunities for competitive solutions and a more efficient industry."

In the nanotechnology area, SEMI has combined its NanoForum conference with the NanoCommerce event, sponsored by Small Times Media and the NanoBusiness Alliance, to create a new showcase—NanoCommerce/ NanoForum 2005. The inaugural conference and exposition will take place November 1–3 at the McCormick Place and Hyatt Regency Hotel in Chicago. The first two days will be focused on strategic discussions, with in-depth examinations of specific markets. The final day will be devoted to technical development and integration topics, such as lithography, metrology, deposition, and surface conditioning.

TSMC targets 65 nm

The world's largest semiconductor foundry company will have its first 65-nm devices in production by December. TSMC says low-power versions of the SoC chips will come first, with high-speed and general-purpose versions available in 2006. The company's Nexsys 65-nm process technology has a standard cell gate density that is twice that of its 90-nm process, with an SRAM cell size half that of the current generation and a memory cell size that is 65% smaller than the 90-nm cell. The new technology is also 50% faster than its 90-nm predecessor and has reduced standby power by 20%, according to TSMC.

Process enhancements include the use of strained silicon and nickel silicide; the 65-nm technology is also the third-generation TSMC process to employ low-k dielectrics and the fourth-generation to use copper. Immersion lithography (IML) techniques, developed with ASML, will also play a role for the first time. The first production-worthy 193-nm IML tool was delivered in 2004 to TSMC, which says it provides a greater than 200% depth-of-field improvement over "dry" scanner systems. The new process will be implemented in TSMC's 300-mm manufacturing facilities, Fabs 12 and 14.

Thanks a billion, says Intel

Early in April the one-billionth chip rolled off Intel's Ireland Fab Operations (IFO) 200-mm lines. The milestone came 12 years after Fab 10 produced its first production device in spring 1993 at the Leixlip site west of Dublin. The second 200-mm facility,  Fab 14, opened in 1998 and was merged with the original plant to create the IFO organization. As the only Intel 200-mm site to support all of the company's business groups, the twin production facilities manufacture 65 individual products, three times that of any of the other six Intel 200-mm facilities, and make up one of the company's two largest flash-memory sites, according to Intel Ireland sources. Five different process technologies are in place, spanning the 0.35-, 0.18-, and 0.13-Ám nodes. Intel opened its first 300-mm line on the Irish campus, Fab 24, in June 2004, with the second 300-mm plant, Fab 24-2, under construction and scheduled to ramp production of 65-nm technology in the first half of 2006.

'Demystifying' chipmaking

A just-published book provides some of the simplest language yet for those trying to learn the basics of the IC fabrication process or update themselves on the latest technologies and procedures. Demystifying Chipmaking, coauthored by Richard Yanda, Michael Heynes, and Anne Miller, takes the reader from crystal growth all the way through the various steps involved in wafer processing and test and assembly to encapsulation.

Recent innovations, such as shallow trench isolation and dual-damascene processes, receive careful treatment. Copious sidebars, definitions, and black-and-white figures and photos help the reader grasp the details of the most sophisticated high-tech manufacturing process on the planet. A "science overview" appendix presents the basics of atoms and molecules, gases, chemistry, solids, electricity, and electric and magnetic fields, while a second appendix offers supplemental information on plasma etching to an earlier chapter. A CD-ROM with short video clips and narration is also included. The book is available for $49.95 (plus shipping) through the publisher's Web site at

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