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Yield Analysis/Metrology

Reducing measurement uncertainty using an ultra-low-voltage, critical-shaped CD-SEM approach

Colin Yates and John Haywood, LSI Logic; and Galen Sapp, Dmitry Gorelikov, and Paul Knutrud, Soluris

As the IC industry approaches the 65-nm technology node, decreasing feature size and tightening requirements for dimensional control require a new approach to critical dimension (CD) metrology. Previously adequate approximations are no longer sufficient, and previously insignificant errors are now unacceptable. For sub-100-nm processes, especially advanced logic devices, transistor performance controls the final value of the IC. Transistor speed is a direct function of the gate length, which is controlled by the gate polysilicon line width CD. Each additional nanometer of CD control adds directly to the final value of the circuit.

The photoresists used with 193-nm lithography exhibit significant slimming when irradiated by the electron beam of the critical dimension scanning electron microscope (CD-SEM). Although it is possible to estimate the rate of slimming by examining the changes induced by repeated exposures, the slimming caused by the initial exposure is difficult to quantify with any certainty. The work described in this article confirms that slimming is primarily a function of beam energy and that the use of ultralow energy can reduce slimming to an acceptable level.

The 2004 International Technology Roadmap for Semiconductors maintains that printed-gate CD control should be <4 nm at the 90-nm technology node and 2.5 nm at the 65-nm node. Achieving that goal will not be easy because it involves both process and measurement uncertainty. Moreover, the concept of critical dimension itself is somewhat outmoded, a holdover from previous generations when circuit designs could be considered to be essentially two dimensional. When the width of a feature is much greater than its height, variations in the shape of the edge are insignificant. But current-generation processes often use high-aspect-ratio structures whose shape and width must be tightly controlled to ensure optimal device performance. CD metrology has evolved into critical-shape metrology.

This article examines two sources of uncertainty in CD measurements: the impact of the measurement process on the measurement result and the need to control shape as well as size. While several methods exist for determining feature shape, all of them have significant shortcomings in process control applications. In contrast, this article describes a CD-SEM-based approach that is precise, accurate, and fast.

Resist Slimming

The issue of resist slimming is not new with 193-nm resists. Early generations of 248-nm resists also exhibited slimming. To reduce slimming, resist manufacturers reformulated their products to reduce their susceptibility to the high-energy electrons present during plasma etch. As a result, the new formulations exhibited reduced slimming during CD-SEM measurements.

While resist manufacturers are trying to achieve similar slimming levels with 193-nm resists, meeting that goal is proving to be difficult for several reasons. First, 193-nm resist is optimized to work with small features at the expense of other parameters, such as E-beam sensitivity. Second, advanced logic devices in 90-nm processes require physical linewidths as small as 40 nm. At a 10% precision-to-tolerance ratio, creating such linewidths requires CD control of 4 nm. Third, line-edge roughness has emerged as a limiting factor in circuit performance. Unfortunately, many of the additives that improve slimming behavior during etch and CD-SEM also increase line-edge roughness. Given these competing effects, it may not be possible to eliminate slimming by reformulating 193-nm resists.

In the case of CD-SEMs, it has proven possible to reduce slimming to acceptable levels by reducing the landing energy of the beam electrons. In general, SEM resolution is determined by the size of the spot formed on the sample surface by the scanning electron beam. However, it is generally more difficult to focus low-energy electrons into a small spot than higher-energy electrons. There has been a steady improvement in the electron optical performance of SEMs at low voltages, driven largely by the need of the semiconductor industry to reduce the adverse effects of high beam energies on electronic circuits. However, while it has become routine to operate with accelerating voltages that are <1 kV (CD-SEMs typically operate with beam energies of 600–800 eV), the elimination of resist slimming requires energies in the 100-eV range.

To solve the conflicting requirements of high beam energy for optical performance and low energy to eliminate resist slimming, specialized electron optical systems have been developed. For example, the dedicated ultra-low-voltage CD-SEM used in this study, the Yosemite system from Soluris (Concord, MA), uses high beam energies throughout most of the electron column to maintain optical performance and a retarding field between the final lens and the sample to reduce electron landing energy at the sample surface. Capable of fully automated operation, the tool has landing energies of <100 eV, making it suitable for evaluating resist slimming as a function of landing energy.

Figure 1: Response of a typical 193-nm resist to exposure to an E-beam. Slimming is characterized by a rapid initial phase, followed by a slower intermediate phase and very slow final decay.

Effect of Beam Energy on Resist Slimming. Several studies have investigated 193-nm resists in order to understand the mechanisms behind slimming behavior.1 Figure 1 shows the response of a typical 193-nm resist to exposure to the electron beam.2 The data were collected at beam energies of 500 and 175 eV; all other test conditions were identical. The test results demonstrated that slimming can be characterized by a rapid initial phase, followed by a slower intermediate phase and very slow final decay. A triple-exponential model was developed to explain the experimental data:

where τ1–3—the half-lives of the three phases—are obtained through fitting. Figure 1 demonstrates the excellent fit between the model and the experimental data.

Figure 2 shows the three phases plotted separately.2 It is apparent that most of the observed difference between the high and low voltage values takes place during the first phase. From the metrologist's point of view, the first phase is the most troublesome and important one, since it occurs on a timescale that is comparable to the time required for a single measurement. The first phase exerts its greatest influence in the initial exposure. Moreover, when relying only on CD-SEM measurements, the magnitude of the initial slimming cannot be determined directly, since there is no zero exposure value with which to compare it. Several methods are used to estimate the initial value by applying an offset to the first measured value. That offset is determined by extrapolating backward from subsequent measurements.

Figure 2: The three slimming phases plotted separately. The first phase contributes to most of the observed difference between the high and low voltage values.

Figure 3 compares CD-SEM measurements taken at 175 and 500 eV.2 The figure also includes estimated values for the unexposed CD calculated using various fitting models: exponential, polynomial, power, and linear. Depending on the model chosen, the initial slimming value ranges from 0.9 to 3.3 nm. Regardless of the model chosen, the steep slope of the curve in the region of the estimate tends to amplify any uncertainty in the data points on which the estimate is based.

Figure 3: CD-SEM measurements taken at 175 and 500 eV. Estimated values for the unexposed CD calculated using polynomial, exponential, linear, and power fitting models are also included.

The three phases of the slimming phenomenon are thought to correspond to three different physical processes occurring in the resist. The first and fastest phase is characterized by chemical reactions within the resist that are a direct result of the interaction with beam electrons. These reactions may include chain scission and photo acid generator decomposition. Depending on landing energy, these processes occur within 20 nm of the resist surface, which is the penetration depth of the electrons. These reactions may cause the resist to form an inert skin that is impervious to further electron bombardment. In the second phase, as irradiation by the beam continues, thermal heating occurs, causing solvent to evaporate from the resist and leading to the loss of free volume as a result of annealing. The third phase, which may be so slow that its effect is negligible, probably involves additional solvent loss from tightly bound sites and other longer-term processes.

Strong agreement between experimental results and a slimming model based on the Grun electron range (essentially electron penetration depth) offers strong confirmation that the processes occurring in the first phase are related to direct beam interaction. Figure 4 compares atomic force microscope (AFM) measurements with the Grun slimming model.2 Each AFM data point represents the difference between measurements made before and after CD-SEM measurement. As shown in Figure 5, penetration depth increases from 2 nm at 100 eV to more than 30 nm at 800 eV.3 Since reformulating the resist to reduce slimming may not be as successful for 193-nm resists as for 248-nm resists, the best way to reduce slimming is to perform measurements at the lowest possible landing energy.

Figure 4: AFM measurements compared with a model based on the Grun electron range. Each AFM data point is the difference between measurements made before and after CD-SEM measurement.
Figure 5: Schematic diagram showing how the depth of penetration changes from 2 nm at 100 eV to more than 30 nm at 800 eV.

Effect of Slimming on Poly Lines. To gain insight into the ultimate impact of slimming on circuit elements and to evaluate the amount of slimming that results from the initial CD-SEM measurement, a test was performed to determine the effect of performing a single measurement on the CD of subsequently etched features. An experiment was designed that compared poly linewidths from regions where the resist was measured using CD-SEM with nearly adjacent regions that were not measured. While etched polysilicon lines are not slimmed by exposure to an electron beam, the electron beam slims the resist, which affects the poly lines.

The investigation also sought to confirm that landing energy, and not another electron-beam exposure parameter, is the primary contributing factor to beam-induced slimming. Consequently, beam energies of 100, 200, 300, 500, and 800 eV (at beam currents of 20 and 40 pA) were examined. The number of integration frames was varied from 48 to 64 to 96 to 128 to 256. All resist exposure regions were separated by at least 3 Ám, and care was taken to avoid exposing other resist regions to the beam inadvertently. All postetch measurements on the polysilicon were performed under the same conditions: a landing energy of 500 eV, a beam current of 20 pA, and 64 integration frames.

As expected, slimming of the resist translated directly into slimming of the etched poly lines. Figure 6 summarizes the results for all currents and frame exposures.4 The use of a 100-eV landing energy resulted in slimming of slightly more than 1 nm, which was 5 nm less than that caused by using an 800-eV landing energy. ANOVA analysis of all experimental variables confirmed that landing energy has the greatest influence on slimming.

Figure 6: Summary of resist slimming results for all currents and frame exposures. Operating at 100 eV reduced slimming to slightly more than 1 nm, which was 5 nm less than at 800 eV.

Critical Shape Metrology

In sub-100-nm processes, feature shape can be as important as width. For example, during gate formation, the overlying polysilicon line masks the gate region during the implant step that forms the source and drain contacts. Although the width of the line remains the primary determinant of gate length, the slope of the side wall has a significant effect on the contours of the implant and can play a critical role in determining device performance. Hence, the need to use shape metrology will become more important as gate structures shrink and become more complex.

All CD-SEMs work by extracting a measurement from the signal-intensity profile as the beam scans across the feature. Protruding features such as edges tend to generate higher signal levels than flat or recessed features. Thus, when CD-SEM was developed as a metrology technique, the bright edges of lines were convenient—and presumably accurate—indicators of the physical position of the edge. SEMs typically have spatial resolution of a few nanometers. When CDs were hundreds of nanometers, errors of a few nanometers were insignificant. However, as gate CDs have shrunk to the 40-nm range in 90-nm advanced logic applications and will shrink further to 30 nm at the 65-nm node, every nanometer is critical.

CD-SEM resolution will always be limited, and conventional CD-SEM algorithms are not sufficient for characterizing the true profile of a feature. The shape of an edge affects the shape of its intensity profile, and proper analysis can extract shape measurements from the signal. Conventional CD-SEM algorithms derive an arbitrary relative value from the intensity profile to indicate edge position. Several different values are used, the most common of which are the point of maximum slope and the point at which the profile reaches a fraction of its peak value (e.g., 50%). Although these values tend to be highly precise for defined-edge shapes in >100-nm processes, they are not accurate if the edge shape varies or in sub-100-nm processes.

Generally, an SEM's highest-resolution signal is the secondary electron signal, which consists of sample electrons that are scattered by interactions with beam electrons. Secondary electrons have very low energy (<50 eV). Although they may be created anywhere within the interaction volume (the region that can be reached by scattering beam electrons), they can escape only if they occur within a few nanometers of the surface. On a flat sample, most secondary electrons in the detected signal are formed immediately below the beam spot, giving the signal its high spatial resolution. Topography is the primary source of contrast in secondary electron images.

For example, protruding features appear bright because their shape brings more of the surface within the secondary electron escape range of the interaction volume. For extreme topographies, such as the sharp edge of a photoresist line, many of the added secondary electrons originate from points that are within the interaction volume but well outside the beam spot. Hence, both the size of the spot and the size of the interaction volume determine effective CD-SEM resolution (as shown in Figure 5). Lower landing energy reduces the size of the interaction volume and improves the correspondence between the intensity profile and the physical profile.

Regardless of the landing energy, the intensity profile that is generated as the beam scans across an edge represents a convolution of the physical edge profile, the distribution of electrons within the beam, and the distribution of primary electrons in the interaction volume. To extract the physical profile from the intensity profile, the CD-SEM signal must be deconvoluted using a Monte Carlo–based simulation method that is based on the physics of the interactions. The Soluris critical-shape metrology (CSM) algorithm was used in this work to create a library of profiles based on a range of input parameters that were specified by the operator. The system searched the library to find a match for the detected intensity profile and reported the dimensions of the corresponding physical profile.

The accuracy of the algorithm for identifying the shape of edge profiles on etched polysilicon lines was evaluated by comparing CSM measurements with focused ion beam (FIB)/SEM cross sections. A trapezoidal model was used to represent feature shape while allowing foot length, sidewall angle, and top-corner rounding to vary. In this evaluation, left and right edges were matched independently to improve matching speed. However, as feature sizes continue to shrink, it will become necessary to match both edges together to accommodate the interaction between them.

Three wafers were prepared with a 130-nm etched polysilicon layer on silicon oxide. Etch conditions were varied for each wafer to produce challenging samples with varying profile shapes and sidewall angles for the CSM analysis. The wafers were first measured using a Yosemite CD-SEM and then measured again using an automated FIB/SEM.

Approximately 330 die were measured on each wafer using the CD-SEM's CSM algorithm, while 10 sites were measured on each wafer using the FIB/SEM. An additional 160 measurements were performed on one of the wafers using the FIB/SEM. CD-SEM images were obtained at 500 V, and FIB/SEM images were obtained at 2 kV. Integrated FIB analy-sis software was used to extract the poly line geometry from the cross-section images.

Extrapolated top and bottom measurements were made using the 20-point measurement and regression scheme illustrated in Figure 7.5 The top was calculated at the top of the line dome, and the bottom was calculated at the gate oxide. Both left and right sidewall angles were measured, while the thickness of the poly was measured from the top of the gate oxide to the top of the feature using waveform analysis. Based on those data, the bottom CD was measured at the top of the gate oxide and at a point 5 nm above that. The top CD was measured at a point coincident to the peak of the feature and between points extrapolated from the sidewall angles. Top CD was also measured 5 nm and 10 nm below that measurement point. A final CD measurement was taken at the vertical midpoint of the feature.

Figure 7: Extrapolated top and bottom measurements made using a 20-point measurement and regression scheme. The top was calculated at the top of the line dome and the bottom was calculated at the gate oxide.

As shown in the Figure 8a images, wafers A and C had sidewall angles typical of features that might be encountered in production. Wafer B, which had a profile with low sidewall angles, was used to test CSM performance under extreme nonnormal conditions. The microtrench along the etched lines was an unexpected by-product of the perturbations in the etch process. In general, the agreement between FIB and CSM results was better for wafers A and C than for wafer B. Reported differences between the sidewall angles on wafers A and C ranged from 1.3° to 0.1°, while the difference between the sidewall angles on wafer B was 4°. Similarly CSM measurements of extrapolated top and bottom CDs showed better agreement with FIB measurements for wafers A and C than for wafer B. Deltas for top and bottom CD ranged from 3 nm on wafer C to 9 nm on wafer A. On wafers A and C, CSM measurements showed consistently better agreement with FIB measurements than with conventional maximum slope CD measurements. At up to 14 nm, the difference between FIB and maximum slope CD measurements on wafer A was nearly twice as large as the difference between FIB and CSM measurements.

Figure 8: FIB cross-sectional images (a) showing overetch of the feature through the gate oxide with a microtrench depth up to 15 nm below the oxide level; and (b) a layer of metal deposited over the line to protect it during milling.

Wafer B had a bottom CD delta of 3 nm and a top CD delta of 12 nm. Several factors may explain the larger top CD and sidewall-angle deltas. First, these lines are more triangular than trapezoidal and have an extrapolated top CD of approximately 7 nm as measured by FIB. At that size, it may not be valid to treat the edges independently, since the signal from one edge may be affected by the signal from the other. Second, the "necking" visible near the top of the line may introduce error into edge detection and the extrapolation of the FIB and CD-SEM analysis. Third, the simulation and matching library were optimized for the more-severe angles typically encountered in production devices.

In comparing the FIB and CSM measurements, the inherent undersampling of the FIB cross-section technique and the effects of line-edge roughness must be taken into consideration. The once-per-site FIB measurements are approximately 3 to 10 times less precise than CSM measurements. CSM measurements represent an average of many profiles acquired along a 1-Ám segment of a line. The 160 FIB measurements on wafer A exhibited a CD variability of 9.4 nm and sidewall-angle variability of 5.4°. The corresponding CSM values were 4.2 nm and 1.2°. Linewidth roughness, estimated at 7.4 nm, is an additional source of variability.

Conclusion

Dimensional control requirements for sub-100-nm processes are beginning to outstrip the capacity of conventional CD metrology. CD requirements are at the 4-nm level, while 2.5-nm CD requirements are on the horizon. Improvements in dimensional control translate directly into improved device performance and increased revenues. Resist slimming and uncontrolled variations in shape are two important sources of uncertainty. Hence, the integration of advanced CD-SEM technology and ultra-low-voltage operation to reduce slimming and the use of critical-shape metrology to achieve 3-D shape control promise to reduce CD-SEM uncertainty without compromising measurement throughput.

References

1. T Kudo et al., "CD Changes of 193-nm Resists during SEM Measurement," in Proceedings of Microlithography 2001 4345 (Bellingham, WA: SPIE, 2001), 179–189.

2. N Sullivan et al., "Electron Beam Metrology of 193-nm Resists at Ultralow Voltage," in Proceedings of Microlithography 2003 5038 (Bellingham, WA: SPIE, 2003), 618–623.

3. G Sundaram et al., "Low Impact Resist Metrology: The Use of Ultralow Voltage for High-Accuracy Performance," in Proceedings of Microlithography 2004 5375 (Bellingham, WA: SPIE, 2004), 675–685.

4. C Yates et al., "Characterization of E-Beam Induced Resist Slimming Using Etched Feature Measurements," in Proceedings of Microlithography 2005 5752 (Bellingham, WA: SPIE, 2005), 510–515.

5. D Gorelikov et al., "Application of Critical Shape Metrology to 90 nm Process," in Proceedings of Microlithography 2005 5752 (Bellingham, WA: SPIE, 2005), 489–498.


Colin Yates works as a photolithography development engineer in LSI Logic's wafer fabrication facility in Gresham, OR. He has been with the company since 1989. He holds four U.S. patents. (Yates can be reached at 503/618-5305 or cyates@lsil.com.)

John Haywood works on etch development at LSI Logic. He has 20 years of experience in the semiconductor industry in the areas of photolithography and etch. Before joining LSI Logic, he worked at Intel. He holds several U.S. patents and has other patents pending. He received a degree in physics from the University of Manchester, UK. (Haywood can be reached at 503/618-3677 or jhaywood@lsil.com.)

Galen Sapp is a senior applications engineer at Soluris. She began her CS-SEM metrology career at IVS in 1985 and has continued to work in this area ever since. She received a BS in chemistry from San Francisco State University. (Sapp can be reached at 415/664-5393 or gsapp@soluris.com.)

Dmitry Gorelikov, PhD, is a senior scientist at Soluris (Concord, MA). His primary interest is Monte Carlo simulations of electron beam–sample interactions in CD-SEM. He received an MS in metallurgy from the Moscow Steel and Alloys Institute and a PhD in materials science and engineering from Northwestern University in Evanston, IL. (Gorelikov can be reached at 978/318-4116 or dgorelikov@soluris.com.)

Paul Knutrud is technical marketing manager at Soluris. He began his metrology career in 1983 as an applications engineer at IVS and rose to director of marketing at Schlumberger. He holds a patent in overlay metrology and has authored more than 10 publications in the field. He received a BSBA in management From Babson College (Wellesley, MA) in 1983. (Knutrud can be reached at 978/318-4041 or pknutrud@soluris.com.)


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