removal, selectivity, substrate damage top list of surface
the May Hot Button, the experts weighed in on what they saw as the critical
topics facing the industry in back-end-of-line (BEOL) surface preparation.
This issue's discussion focuses on the related yet distinct problems in
the front end of the line, where the cleaning, stripping, and conditioning
challenges at the 65-, 45-, and 32-nm tech nodes are at least as daunting
as those seen in the interconnect process sequences. How can postgate
cleans be nondamaging, provide excellent uniformity results, and hit their
cleanliness specs? What combination of wet and dry photoresist strips
will work best to maintain dose levels and leave ever-thinner feature
structures intact? How difficult will high-k dielectric materials be to
clean and prepare? Can megasonics be improved and extended, and will supercritical-carbon-dioxide
cleaning ever become a mainstream process? These questions and more are
addressed by this month's panel of experts from the chipmaker, research,
OEM, and materials communities.
GALE (vice president, FEOL cleaning project, SEZ) and HARALD OKORN-SCHMIDT
(vice president of global R&D, SEZ): If asked to come up
with a single word to characterize the current issues in front-end-of-line
(FEOL) cleaning, stripping, etching, and surface-preparation processes,
we would still say selectivity. On the one hand, the already-stringent
defect-density requirements will extend into the 45-nm node and beyond.
But in addition, the introduction of novel, sensitive substrates and materials
such as strained silicon, high-k dielectrics, new silicides, and maybe
even metal gates—partly being implemented or close to being introduced
into manufacturing—underscore the need for fresh solutions with
well-controlled selectivity among materials and structures.
the area of photoresist stripping, plasma-based processes have been used
for many generations to break through the carbonized crust of heavily
ion-implanted resist with adequate success. For future device generations,
however, these dry ashers are in principle out of the game because of
the intolerable substrate damage they create, which is the root cause
for significant substrate loss in the subsequent cleaning step. Hence,
the industry is challenged to find a new way to "dissolve" the resist
without damaging, etching, or significantly oxidizing the underlying materials.
An all-wet process, accommodating preferred integration schemes, would
be an ideal solution.
the number-one FEOL challenge is how to selectively remove nanometer-sized
particles without damaging nanometer-sized device structures with aspect
ratios of 5:1 and higher—and doing it with nearly zero substrate
loss/etching. The 2004 update of the International Technology Roadmap
for Semiconductors states that for the 45-nm node, the target is the removal
of 22.5-nm particles, with a maximum loss for silicon or oxide of no more
that 0.04 nm per cleaning cycle.
the past 15 years, significant R&D has been carried out at corporate
and academic research centers to show that the SC-1 cleaning step requires
some substrate etching to remove particles when the process relies exclusively
on chemical action. At some point, megasonic cleaning was introduced in
order to mechanically enhance particle removal. In terms of physical and
forces, this made perfect sense—and it still does. One critical
issue facing the industry, however, is that manufacturers of these systems
have not adequately understood the process and cleaning-mechanism fundamentals.
For a long time, such understanding was probably not necessary, as the
commercially available systems did the job.
around the 130- to 90-nm nodes, all the systems began to create serious
device damage. This stimulated a few research centers to seriously investigate
the science behind megasonic cleaning. As a result, a wealth of new insight
has opened exciting possibilities for the control and optimization of
megasonic systems—not only the physical/mechanical aspects, but
also the further optimization of the chemistry itself. In the not-too-distant
future, particle-removal selectivity can be expected to reach a new dimension
involving optimized chemistry supported by physical/mechanical "massaging."
MERTENS (program leader, ultraclean processing program, IMEC):
Never in the history of IC manufacturing have there been so many critical
cleaning issues. Particular combinations of specifications for cleaning
processes cannot be fulfilled but rather end up in complex specification
FEOL, postgate cleaning has become a major concern. There is no known
cleaning method that can meet the very tight silicon-recess specifications
and provide a good cleaning performance that does not damage fine gate-electrode
structures. The use of megasonic systems for these critical applications
suffers from severe non-uniformity and damage related to the cavitation-driven
cleaning process. Through a more fundamental understanding of megasonics,
these systems can be significantly improved. At the same time, various
kinds of high-velocity aerosol-cleaning processes are under investigation
as alternatives to megasonic agitation.
sub-45-nm technologies, the search is still on for an appropriate
use of sputter cleans prior to nitride deposition for silicides has been
generally found to be too aggressive—because of a lack of selectivity—to
meet the required tight specs on silicon loss for limiting junction recess.
This finding implies that adequate drying techniques that leave no watermarks
will be mandatory.
sub-45-nm technologies, the search is still on for an appropriate surface
passivation that produces a sub-1-nm equivalent oxide thickness as well
as high-quality interface and transistor characteristics. Different integration
schemes are also under investigation for metal gates on top of high-k
dielectric layers, each requiring novel cleaning approaches.
postetch residue removal, the issues are even more complex. In general,
as the low-k dielectric material gets a higher carbon content, the chemical
difference between the residues and the actual low-k material becomes
smaller, which in turn makes selective removal much more challenging.
Therefore, the potential of physically assisted cleaning processes should
be investigated. After plasma exposure, the low-k sidewall often shows
a graded composition from bulk low-k to plasma-modified low-k
to residue. As feature sizes scale down, the interface between the residue
deposited on the sidewalls and the plasma-modified low-k underneath becomes
the low polarizability of these materials results in a contact angle with
water that is significantly larger than that shown with traditional inorganic
dielectric materials such as silicon dioxide. As a result, the stability
of liquid films on these surfaces is reduced, which alters the mechanism
of the drying process needed after a wet clean. Therefore advanced, high-performance
drying methods are required.
use of supercritical carbon dioxide (SCCO2) has been promoted
by several companies as a solution for cleaning of postetch residues of
(porous) low-k dielectric layers. This may not become the killer application
for SCCO2, unless it removes residue without a plasma ash.
Also, the immaturity of the technology has been underestimated. As a result,
several companies and organizations have halted their programs.
the longer term, however, SCCO2 shows great promise for cleaning
certain ultrafine features with high aspect ratios where wet cleans will
have lost their effectiveness. Also, the use of the supercritical process
for low-k repair, air-gap fabrication, and photoresist development could
prove very valuable. Much more research on the fundamentals of this important
technology—such as chemical residues and background particle, metallic,
and organic contamination—is required.
T. MO (FEOL logic process development, semiconductor R&D center, IBM
Systems and Technology Group): The key challenges facing the
surface-preparation community include photoresist strip, particle detection
and removal, and critical interface control. As devices employ ever-shallower
junctions with lower-energy and higher-dose implants, resist strip becomes
more difficult because of the formation of a carbonized crust. Feature
sizes decrease and aspect ratios increase with each technology node, adding
another layer of complexity to the problem. Dose loss, feature damage,
and incomplete removal are the challenges for dry strip. Aqueous batch
strip must maintain a complete strip over a variable batch size and bath
life, and aqueous single-wafer strip must minimize chemical usage and
needs to be a new type of tool that bridges the gap between aqueous
cleaning and deposition.
a development facility such as IBM Fishkill, technologies are developed
that include a variety of feature sizes and pattern densities in which
resist and implant dose and energy are frequently changed as the technology
matures. These are inherent aspects of technology development, yet tooling
decisions must be made at least a year before the technology is developed.
While the vendors do an excellent job of explaining the resist-strip capability
of their tools, we want to see how well the equipment will perform on
our own products. Demonstrations can provide valuable insights, but the
difficulty lies in translating the effect of a single resist-strip demo
on existing products to the day-to-day performance on products with still-undecided
dose and energy ranges and yet-to-be-built features.
detection and removal also gain importance with scaling. The standard
particle size detected for tool monitoring is around 100 nm, however the
nominal gate length of most products is significantly smaller. A routine
method for monitoring particles with diameters about half the nominal
gate length is definitely needed. With decreasing feature sizes come thinner
films and lower film-loss budgets, especially for silicon-on-insulator-based
devices. Since the use of aggressive chemistry to remove particles is
no longer a viable solution, physical removal has become more important.
Although the industry is well aware of these problems and hard at work
to solve them, the necessity of this work must be emphasized.
technologies under development require unusual materials and thinner films
than those used in previous generations. This trend provides new opportunities
for the surface-preparation community to contribute to the product, not
just in the traditional contamination-removal sense, but also in the way
critical interfaces and monolayers are prepared. Although aqueous chemistry
will likely remain the predominant method of true FEOL cleaning applications,
surface preparation should not be limited to this approach. One obstacle
to this new concept is the flexibility of most toolsets. In order to capitalize
on this opportunity, there needs to be a new type of tool that bridges
the gap between aqueous cleaning and deposition. From a process development
perspective, what is needed is a toolset that can easily test the capability
of a variety of chemistries to find the correct application for each approach.
STARZYNSKI (surface preparation and materials integration R&D, Honeywell
Electronic Materials): Driven by the need for higher-density
devices, many leading IC device makers are looking to high-k materials
to enable higher current density by minimizing current leakage through
the transistor gate. The incorporation of these high-k materials as gate
dielectrics will result in a paradigm shift in semiconductor manufacturing.
High-k dielectrics are not compatible with existing polysilicon gate materials.
The entire gate structure as well as the associated surface preparations
will need to be replaced.
current gate dielectric is formed by the controlled oxidation of a cleaned,
hydrogen-terminated silicon surface. The high-k dielectric film will be
deposited, probably by atomic-layer deposition techniques, on top of an
ultrathin (3–4-Å thick) silicon dioxide layer. In air, a silicon
surface will spontaneously grow a native oxide layer that is approximately
15 Å thick. Hydrogen termination of the silicon surface will prevent
the growth of native oxide for several hours. It is not clear how an ultrathin
SiO2 layer, much thinner than a native oxide layer, can be
precisely and routinely grown.
the gate electrode is formed, the high-k dielectric will need to be removed
from the source and drain regions of the transistor. Most likely, this
will be accomplished by a combination of sputter-etching and wet etching.
This high-k wet etchant must possess elevated high-k film selectivity
to silicon, to gate materials, and to isolation oxide etch.
development of a selective high-k etchant has been complicated by the
presence of several potential high-k dielectric films. Hafnium oxide (HfO2),
hafnium silicates (HfxSiyOz),
and nitrided hafnium silicates (HfxSiyOzNw)
are all candidates. A wet etchant developed for one high-k film might
not be the optimal etchant for other similar films.
architecture of the gate electrode that will be used in conjunction with
the high-k dielectric has not been finalized. Fully silicided gates such
as NiSi2, metal sandwich gates such as Ru/TiN, and metal-poly
gates such as doped Si/TiN are all under active consideration. The surface
preparation techniques required to produce these electrodes will have
to be developed.
migration to high-k gate dielectrics results in the replacement of not
only the gate dielectric, but the gate-electrode architecture and materials
as well. Surface treatments will need to be developed in order to integrate
these new films into the manufacturing process. In addition, high-k wet
etchants as well as techniques to grow ultrathin SiO2 will
be needed. The transistor gate, which determines device performance, will
be radically altered. The risks are enormous.
are numerous materials and processing questions that need to be answered.
What high-k material will become the dominant gate dielectric? What materials
and processes will be needed to form these new gate electrodes? What etchants
and surface preparation chemistries will be used to fabricate these new
transistors? It is not surprising that the incorporation of high-k gate
dielectrics into IC manufacturing has taken much longer than originally
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