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Manufacturing Effectiveness Series

Meeting manufacturing metrology challenges at 90 nm and beyond

Benjamin Bunday, Milton Godwin, Pete Lipscomb, Dilip Patel, and Michael Bishop, International Sematech Manufacturing Initiative;
John Allgair, Freescale Semiconductor assignee to Sematech; and Alain C. Diebold, Sematech

Integrated device manufacturers will face many defect and lithography metrology issues as manufacturing moves to the 90-nm node and below. The optical defect-inspection tools that are currently available do not adequately detect defects at 90 nm and beyond, while scanning electron microscopes (SEMs) are too slow. With each successive technology node, critical dimension (CD) metrology measurements are becoming more difficult as the industry nears the limits of CD-SEM and optical critical dimension (OCD) measurement capability. In addition, new overlay metrology, optical, and SEM methodologies will be required to replace traditional box-in-box overlay targets, which lack the accuracy required in the device patterning process.

Defect detection and lithography metrology projects by the International Sematech Manufacturing Initiative (ISMI) are aimed at accessing and improving the manufacturing worthiness of measurement equipment. The first step toward determining manufacturing worthiness is evaluating existing equipment using a standardized set of test wafers and consensus criteria or specifications that are based largely on the International Technology Roadmap for Semiconductors (ITRS). The evaluations have shown that the ability of existing toolsets to perform defect detection and lithography metrology is limited.

This article reviews some of the major manufacturing challenges facing defect and lithography metrology at future technology nodes. In addition to describing patterned-wafer defect-detection tools, it compares state-of the-art equipment to ITRS requirements and explores future directions. Finally, it explores both CD and overlay metrology.

Defect Metrology

Bright-field, dark-field, and SEM-based tools are the most widely used systems for patterned-wafer defect detection. All three use die-comparison techniques to identify differences as potential defects. They differ most basically in their sources of illumination and associated detectors.

Defect-detection equipment can be categorized according to the type of illumination and receiving sensors they use. Most bright-field detection tools are illuminated by lamps that emit various wavelengths of visible and near-visible light. The trend is for this illumination to use shorter wavelengths to improve discrimination and enable detection of smaller defects in decreasing pattern pitch.

Bright-field tools use charge-coupled-device detection arrays that form a pixel image of an area of interest on a semiconductor wafer. Images of similar areas on adjacent dies are compared pixel by pixel to determine differences among the dies. To suppress unwanted noise resulting from changes in coloration or slight variations in line edges, digital filters can be constructed and employed in the comparison (difference) map. Following review, difference patterns are identified as defects of interest as the entire wafer is scanned. To compare images accurately, superior focus is required. Therefore, a bright-field scan represents a precise z plane with little depth of focus.

Dark-field detection tools use laser illumination at various wavelengths. Historically, lasers with shorter wavelengths of light have demonstrated less-powerful illumination capability than lasers with longer wavelengths. Various system designs have tried to accommodate for the loss in discrimination with increased radiation per square area, thereby providing more reflective information on defects of interest. Simultaneously, laser development and detection sensitivity tend to overcome limitations in lasers with shorter wavelengths. For example, an illuminating laser can be placed at various angles of incidence to accommodate suppression of surface noise. Detectors in dark-field systems are photomultipliers that are placed at oblique angles of reflection in relationship to the wafer surface. The choice of incoming angle of laser illumination and receiving angles of reception are based on what the tool designer considers the most likely causes of noise. Noise confounds the signal coming from outcropped or concave disruptions of the surface associated with defects of interest.

However, as design rules shrink, the wave properties of the visible and near-visible light deployed in both bright- and dark-field systems interact with device layouts as if the layouts were diffraction gratings rather than distinct features. Reflectance lobing from structures that were previously resolved as straight edges imposes resolution issues and noise that are difficult to overcome, impeding the tool’s ability to differentiate between signals from defects of interest and nuisance defects.

Coming into increasing use in the defect-detection area, SEM offers greater resolution than bright- or dark-field instruments. While its 1-nm electron wavelength is shorter than visible light, SEM detection is unfortunately hampered by scanning speeds that are associated with more-discriminatory illumination methods, a problem that is exacerbated by growing wafer sizes. Furthermore, SEM is conducted in a vacuum. The reliability of vacuum chambers containing SEM columns is considerably less than that of optically illuminated systems.

Challenges Facing Defect Detection and Characterization. As highlighted in Table 112a (“Defect detection technology requirements—near-term”) in the yield enhancement chapter of the ITRS, improved resolution down to a 0.5× feature size is required for in-line defect detection.1 Detection of very small defects on both patterned and unpatterned wafers at the 45-nm node and below is of particular concern.

With each successive design node, bright-field wafer-inspection technology becomes increasingly less capable of meeting the defect-detection challenge. Furthermore, IC manufacturers do not know what types of hardware and software can extend the technology to future nodes. While E-beam inspection offers higher resolution than the bright-field method, it has very low throughput.

With bare-wafer inspection, the detection of defects that are smaller than local surface roughness will be needed. This need can be met using a wide variety of thin films, but the challenges are most severe on very rough surfaces. In the defect review and characterization areas, the redetection and in-line elemental analysis of defects that are <100 nm in size remain a challenge.

As defects of interest shrink along with ground rules, yield learning relies heavily on the ability to detect defects in-line and to redetect defects using SEM review tools. Investigators are not confident that SEM review tools will be able to redetect defects quickly and reliably, especially when cosmetic surface variability will compete with true defects of interest. In addition, increasing costs are a major concern as the industry moves from optical to E-beam inspection. Early technical breakthroughs are needed to mitigate costs. Coordination among suppliers, researchers, and independent device manufacturers is needed to define the metrics, methods, and test vehicles required to meet the ITRS.

Possible Solutions. ISMI projects address many of the challenges facing defect metrology. In the area of patterned-wafer inspection, ISMI has developed intentional defect array (IDA) wafers to evaluate and enable the development of advanced defect-detection and review tools. IDA wafers have been developed for 65- and 35-nm design rules with defect sizes down to 9 nm and more than 10 types of defects. These wafers are characterized and tested on the latest defect-detection and review tools. Example defects are shown in Figures 1a and 1b.

Figure 1: Intentional defects to test detection and review tools: (a) a 9-nm bridging defect structure on a 35-nm gate-level structure, and (b) a 22-nm line-end extension in the x direction in a 65-nm MI trench.

For unpatterned-wafer inspection, ISMI has developed standard wafers with future-generation film and polystyrene latex (PSL) spheres as small as 20 nm. PSL spheres are used to simulate defects of known size during sizing calibration. Figure 2 shows the PSL layout on an unpatterned test wafer. Such test wafers are employed to evaluate tools and to gain understanding of defects associated with new materials for the sub-45-nm technology node and beyond.

Figure 2: Layout of PSL deposition on unpatterned test wafer.

ISMI is also conducting a study to isolate the sources of errors that cause false defects during review. Specifications will be developed and results will be communicated to suppliers of defect inspection and review equipment to improve automated defect review.

As chipmakers strive to achieve higher yields at the wafer periphery, ISMI has initiated a project to create standards for bevel-edge inspection. The initiative is guiding the supplier community to optimize the definition of inspection areas, sensitivity, and data integration of bevel-edge inspection.

Finally, ISMI is engaged in the Yield Council and Defect Metrology Advisory Group, where yield managers from ISMI member companies meet to share best-known methods and establish program direction for critical areas of concern in the defect inspection field. ISMI also works closely on the yield enhancement chapter of the ITRS.

Lithography Metrology

With shrinking on-chip CDs, especially gate widths and contact-hole diameters, state-of-the-art CD metrology tools have had difficulty keeping pace with the stringent lithographic and etch CD measurement requirements in cutting-edge device fabrication facilities. The tight CD and overlay control requirements for 90-nm technology and beyond appear in Table 117 of the ITRS (“Summary of 2004 ITRS CD and overlay metrology requirements”).1 Three-sigma metrology of at least 0.2 nm will be needed for the 32-nm node in 2013. As with previous technology generations, the industry will likely achieve that node well before the target date.1

Two well-known technologies are used to perform lithography metrology: CD-SEM and optical scatterometry (also known as OCD), both of which have found their way into volume production.

CD-SEM. CD-SEMs are microscopes that map a target with a focused, rastered electron beam. Figure 3a presents a schematic diagram of a basic SEM optical column. An electron gun generates electrons of various energies. This electron “beam” is accelerated to several kilovolts of energy down an optical column, which is made “monochromatic” using an aperture, focused with multiple electrostatic objective lenses, and steered over the target using electric or magnetic fields. Then the beam is decelerated so that the energy is on the order of hundreds of volts. The final beam spot size is approximately 10 nm. Typically, the beam is TV-rastered over the target. The beam interacts with the target, generating many secondary electrons and backscattered electrons at the point of impact and within the interaction volume, as shown in Figure 3b. CD-SEMs use secondary electrons because they have low energy and thus have a very shallow escape depth from the sample, which is important for quality surface imaging. As illustrated in Figure 3c, many secondary electrons can escape from feature edges and corners, which is useful for edge detection.

Figure 3: Schematic diagrams showing (a) a basic SEM column, (b) electron beam interaction volume with a sample, and (c) secondary electrons escaping from feature edges. 2

As the beam is scanned over a field of view (which is inversely related to magnification), a detector collects the secondary electrons from each pixel so that an intensity map is generated. Depending on the column design, different schemes of sample grounding/bias or electric/magnetic “extraction fields” can be employed to reduce sample charging or increase secondary-electron collection efficiency. An intensity function (waveform) is produced from each linescan; various signal processing (filtering) and mathematical constructions (edge-detection algorithms) are applied to these waveforms to assign edge locations. CDs, roughnesses, or other metrics can then be derived from the raw edge data.

According to evaluation results obtained by the Advanced Metrology Advisory Group (AMAG) of ISMI/Sematech, current-generation CD-SEMs can achieve ~1.5-nm image resolution at beam voltages from 2 kV down to 100 V, with apparent beam widths of ~9 nm. Precision/reproducibility (3σ of multiple measurements of the same feature) is ~0.4 nm on etched silicon line samples and ~1.3 nm on argon fluoride (ArF) photoresist line samples (or ~0.4 nm if the infamous ArF resist-shrinking trend is removed). In contrast, contact-hole measurement is more difficult, with precision approximately 40 to 50% larger than that of line samples. CD-SEM pattern-recognition features have improved to the extent that during testing, it was difficult to make a system fail without varying the process window extremely.

Some CD-SEM systems use interferometers for navigation, allowing navigation tolerances to fall below 100 nm. Pipeline throughput (five sites per wafer) can be higher than 70 wafers per hour, with a move-acquire-measure (MAM) time of ~3.5 seconds under full operator-free automation. Resist shrinkage during first measurement, which is tested using CD atomic force microscopy before and after E-beam exposure, results in linewidth shrinks of ~2 nm. Accuracy, or total measurement uncertainty, values of 2 nm are achievable, despite the long-observed CD-SEM measurement bias, where CD-SEM linewidth measurements are several nanometers larger than those from reference systems.

Major issues for future attention should include further improvement of ArF resist shrinkage, contact hole imaging, navigation matching between tools, accuracy, and roughness measurement (including line-edge roughness and linewidth roughness). While CD-SEMs are effective tools for measuring linewidth roughness and meet current ITRS needs, standardization of measurement techniques and calibration across the industry is an important but elusive goal.3-5 Examples of CD-SEM’s capabilities are shown in Figure 4.

Figure 4: CD-SEM images: (a) an 18-nm etched gate demonstrating CD-SEM's viability at the 45- and 32-nm nodes, (b) rough resist lines demonstrating CD-SEM's high imaging resolution, and (c) a NIST RM8091 resolution sample.

As imaging tools, CD-SEMs are very flexible. They can measure isolated, dense features in nonregular circuits or in a grating. However, because standard top-down CD-SEMs use “line-of-sight” optics, they cannot see the bottoms of reentrant features. This limitation has been ameliorated somewhat by the addition of a tilt-beam, a beam that is bent electrically or magnetically in the column so that imaging is achieved at a small tilt angle—for example, 5–15°, as illustrated in Figures 5a and 5b. Using the tilt-beam modification, two images can be taken at two different tilt angles, enabling users to calculate profile heights and sidewall angles. It has been shown that this technique is useful on features down to ~100 nm wide.6 While further experiments will explore the technique’s ability to image even smaller features, it is anticipated that improvements will be needed for it to be competitive with other profile-measurement methods.

Figure 5: Images of a resist line at (a) 5° and (b) 15°. Edge widths from these images can be used to reconstruct the height and sidewall of the resist profile.

Traditional CD-SEMs have another drawback: they
sample only a single feature at a time. Because of feature-to-feature variations, single-feature sampling may not provide a good estimation of a process’s true average CD. However, the most recent CD-SEMs can measure multiple features within the same image without affecting speed, enabling the measurement of local process averages and variances. This feature greatly improves CD-SEM’s ability to perform process control and characterization. In effect, the new capability, which results from improved image processing and a larger field of view without sacrificing information/pixel density, collects an order of magnitude more information per unit time than previous-generation CD-SEMs, offering a new paradigm for future CD-SEM metrology.7

A new trend in CD-SEM technology is automated recipe setup.8 This feature, which enables users to input CAD files (e.g., in gds format) with flagged measurement locations from which the tool writes recipes for measuring targets, is useful for characterizing and monitoring optical proximity correction (OPC) in a circuit. While an engineer may spend days writing a 1000-target recipe that may only be run once, the automation of this task frees up the tool to run more iterations of these measurements.

Optical Scatterometry (OCD) Tools. Scatterometer (OCD) tools are variations of the spectral ellipsometers and reflectometers used for CD metrology. They function by collecting the spectra of reflected photons from a grating target. The principle of scatterometry is illustrated in Figure 6. The target structure consists of a flat substrate that can contain a multilayer thin-film coating with a line-space or contact grating on it. A collimated beam of light is directed onto the grating. The width of the beam is large enough to cover at least several tens of periods of the grating.

Depending on the period of the grating and the wavelength of the incident light, a number of diffracted orders may reflect from the grating. The 0th order is defined by the light that is reflected as if the substrate were totally flat, satisfying the equality θr = θi, where θr is the angle of the reflected beam and θi is the angle of the incident beam with respect to the vector, which is normal to the substrate plane. If the incident light intensity is Ii and the reflected light intensity is Ir, then reflectance, R, may be defined as

R, which depends on the physical target structure and the properties of the incident light beam, is a strong function of grating period (pitch), grating geometry, linewidth or contact hole CD and profile, grating refractive index, multilayer thin-film coating, the base substrate, incident-light wavelength, angle of incidence, polarization, and azimuth angle. The physical reason for the variation of the reflectance is that the incident light interacts with the grating and any multilayers between the grating and the substrate. These interactions, which are sensitive to angle of incidence and wavelength, cause different amounts of energy to be reflected or absorbed by the substrate and, when possible, to be emitted in other diffracted orders. Variations of these parameters produce their own imprints on R, and the scatterometry method, including both the hardware and the modeling software, must be able to differentiate between the effects of these parameter variations and target profile variations.

The dependence of reflectance on these parameters can be used to characterize the physical properties of the target structure. A periodic target is constructed to simulate the circuit pattern size (design rules) and density to be controlled. Reflectance is measured as a function of the angle of incidence or as a function of the wavelength, while accounting for polarization. That relationship is shown in the raw spectral data in Figure 6.

Figure 6: Schematic diagram of a spectral ellipsometer scatterometer.

The relationship between the reflectance curve and the grating parameters is highly nonlinear and cannot be solved analytically. Typically, the measured curve is analyzed using regression techniques based on Maxwell’s equations or is compared to a library generated using a theoretical model derived from Maxwell’s equations.

While regression techniques have been applied to some applications, their use for multilayer stacks and 3-D applications is somewhat limited because of the computational time required and the susceptibility of converging to local minima, possibly obtaining multiple nonunique solutions. In contrast, theoretical libraries are easier to employ than regression techniques, although they require significant computational time. Library generation is critical to achieving successful measurement results. Theoretical libraries require knowledge of the film stack properties. Film thickness, wavelength-dependent index of retraction (n) and wavelength-dependent extinction coefficient (k) values, and profiles (bottom CD, mid CD, top CD, height, sidewall angle, etc.) are used to generate such libraries. The signature library can be computed using rigorous diffraction-modeling algorithms, which are based on approximations of Maxwell’s equations. Two of the better-known modeling techniques are rigorous coupled-wave analysis and the classical modal method. Accuracy and convergence speed are important practical considerations when choosing a modeling method.

Two essential requirements for comparing a measured reflectance curve to a signature library are sensitivity and uniqueness. If the method must have a measurement resolution of 0.1 nm, it must be able to differentiate, within the constraints of the signal-to-noise ratio, between the fits of two signature curves 0.1 nm apart in the line or contact CD space. Also, within the relevant parameter space, one unequivocal best fit must be assured, so that two totally different results are not obtained from the same measurement.

Other types of scatterometry hardware are used, such as reflectometers, which vary angle but not wavelength, and normal-incidence reflectometers, which vary polarization. While such tools are typically not as capable across the broad band of possible applications as stand-alone spectral ellipsometers, they have cost and size advantages that will enable them to be used in future integrated metrology.

Because OCD tools are diffraction based, the target must be a grating that consists of a single feature repeated with a well-defined pitch. The technique cannot measure truly isolated single lines or more-complex 3-D shapes inside a circuit. However, because of the OCD beam spot size, the technique can sample many features simultaneously, yielding great precision with very high confidence in the estimation of average CD or grating profile. Conversely, since OCD cannot measure roughness and CD variations across the grating, these metrics require imaging tools. In addition, with OCD tools, light penetrates deep into the target’s material stack, so that variations in films buried beneath the surface can potentially interfere with the signatures from the surface grating features.

ISMI’s AMAG is evaluating OCD tools’ ability to image 45-nm gate samples, as illustrated in Figure 7. In general, the tools investigated to date offer 0.4-nm precision for isolated resist and silicon gate lines, 0.1-nm precision for dense resist or gate lines, subnanometer total measurement uncertainty for accuracy, and pipeline throughput of 80 wafers per hour with a move-acquire-measure time of ~4 seconds. Tools not yet tested are expected to exhibit throughput of ~120 wafers per hour and move-acquire-measure times of ~2 seconds. As expected, no resist-shrinkage problem has been observed, as in the case of SEMs, although some resists may exhibit bleaching after UV exposure, large doses of which change n and k values. Tests also show that OCD tools’ beam spot size ranges from 20 to 60 µm. Since precision improves with larger beam spot sizes, there is an advantage to measuring more features with the bigger spot.4,9

Figure 7: Results of ISMI measurement precision of OCD technology (white box) and CD-SEM (colored boxes for various years) on isolated gates. ITRS precision requirements are represented by the red curve.

Overlay Metrology

In the area of overlay metrology, the ITRS states that precision is the only parameter by which overlay performance is measured (see “Summary of 2004 ITRS CD and overlay metrology requirements” table).1 In its investigation of overlay technology, ISMI has reviewed the performance of many different technologies, all of which can potentially meet ITRS requirements for metrology precision through the 32-nm technology node but fail to measure in-device structures directly. Sematech and KLA-Tencor (San Jose) have shown that traditional box-in-box overlay targets display significant inherent instability in the purpose-built overlay metrology target when the metrology system is highly stable.10,11

Work is under way to understand the highly varied contribution that overlay metrology target measurements make to instability.12 The move from traditional box-in-box targets to periodic, or grating-type, structures has led to better measurement precision and potentially greater measurement accuracy than can be achieved through in-device measurements. It has been shown that grating targets result in a 60–70% reduction in measurement precision error over box-in-box targets because of their improved signal-to-noise ratio.11 State-of-the-art overlay measurement systems can perform in the 0.5-nm precision range, which is more than adequate to meet precision requirements down to the 32-nm node.

More important than precision is the ability of the overlay measurement to predict in-device overlay, or overlay mark fidelity. The overlay measurement mark must be resistant to wafer processing variations and should experience the same scanner/lens–induced pattern-placement shift as design-rule structures in the device. Newer grating structures that have been tested in a shallow-trench-isolation process with different chemical-mechanical polishing times are 50% less sensitive to process variation than traditional box-in-box overlay metrology structures.11 The processing-induced error associated with grating structures is on the order of 1 to 2 nm, which is significant considering that the metrology error budget at the 32-nm node is only 1.3 nm.

Another component of overlay mark fidelity involves the pattern-placement shift or error that is associated with the lithographic exposure system. It has been shown that certain device feature sizes experience different lateral translations at the wafer plane. Traditional box-in-box targets, because of their large size, do not experience the same lateral translation at the wafer plane as design-rule device features do. Smaller device features “move around” more than box-in-box overlay measurement targets as a result of lens aberrations. The simple binary image in resist in Figure 8 demonstrates this effect, where the minimum pattern-placement shift or error is 4.64 nm. Under certain exposure conditions, a 6-nm difference has been produced between traditional overlay measurement targets and in-die overlay as measured by SEM, a difference that is clearly too high for the 32-nm node.13 Hence, despite good precision, total measurement uncertainty resulting from overlay issues can lead to yield loss, although the process and metrology themselves are in control.14
Figure 8: SEM-based pattern-placement shift or error (3-σ) measurements at various device locations: PPE 1 = 4.64, PPE 2 = 6.09, PPE 3 = 8.83, PPE 4 = 5.11, PPE 5 = 9.43, PPE 6 = 5.11, PPE 7 = 7.24, PPE 8 = 7.06, and PPE 9 = 4.66.

ISMI is involved in several efforts to ensure capable overlay metrology down to the 32-nm node, including:

• Developing new test structures and methodologies to identify sources of error in the overlay metrology process.

• Testing a newly delivered, fourth-generation overlay test reticle with OPC (see Figure 9). The effects of OPC on pattern-placement shift or error will be investigated.

• Planning a fifth-generation reticle that will utilize chromeless phase-shifting technology, the reticle enhancement technique that investigators believe will be needed for the 45- and 32-nm nodes.

Figure 9: Overlay reticle layout used for PPE calibration and measurement.

These structures and reticles, which will be used to test current and next-generation overlay metrology technologies to ensure that they are 32-nm-node-capable, will be delivered to ISMI member companies to be tested and fine-tuned.

Next-generation overlay metrology efforts also include small-target in-device measurements and optics improvements to measure these targets, diffraction-based measurements, and secondary-electron-based overlay measurements. Finally, work is proceeding on an overlay reference measurement system to enable highly accurate measurements of actual in-device overlays.


ISMI is conducting metrology projects in the areas of defect detection, lithography metrology, and overlay. Its assessments have shown that a number of major gaps must be addressed in next-generation defect-detection equipment. It has also shown that CD metrology equipment can meet the requirements of the 65-nm node. However, overlay metrology still requires new target structures. ISMI will continue to evaluate the manufacturability of defect-detection, CD, and overlay equipment.


The authors wish to thank Sean Hannon of AMD for his assistance in preparing this paper. They would also like to thank Ron Remke of ISMI.


1. The International Technology Roadmap for Semiconductors (San Jose: Semiconductor Industry Association, 2004); available from Internet:

2. AE Vladár, JS Villarrubia, and M Postek, Exploring and Extending the Limits of Critical Dimension Scanning Electron Microscopy (CD-SEM) Resolution, Sematech Technology Transfer Report to Members (Austin, TX: Sematech, 2002).

3. B Bunday et al., Unified Advanced CD-SEM Specification for Sub-90 nm Technology, Sematech Technology Transfer Report to Members (Austin, TX: Sematech, 2004); available from Internet:

4. B Bunday, A Peterson, and J Allgair, “Specifications, Methodologies, and Results of Evaluation of Optical Critical Dimension Scatterometer Tools at the 90nm CMOS Technology Node and Beyond,” in Proceedings of SPIE, vol. 5752 (Bellingham, WA: SPIE, 2005), 304–323.

5. B Bunday, M Bishop, and J Allgair, “Results of Benchmarking of Advanced CD-SEMs at the 90 nm CMOS Technology Node,” in Proceedings of SPIE, vol. 5375 (Bellingham, WA: SPIE, 2004), 151–172.

6. B Bunday, M Bishop, and J Swyers, “Quantitative Profile-Shape Measurement Study on a CD-SEM with Application to Etch-Bias Control and Several Different CMOS Features,” in Proceedings of SPIE, vol. 5038 (Bellingham, WA: SPIE, 2003), 383–395.

7. B Bunday et al., “CD-SEM Metrology Macro CD Technology—Beyond the Average,” in Proceedings of SPIE, vol. 5752 (Bellingham, WA: SPIE, 2005), 111–126.

8. C Tabery et al., “Design-Based Metrology: Advanced Automation for CD-SEM Recipe Generation,” in Proceedings of SPIE, vol. 5752 (Bellingham, WA: SPIE, 2005), 527–535.

9. B Bunday et al., Unified Advanced Optical Critical Dimension (OCD) Scatterometry Specification for Sub-90 nm Node Technology, Sematech Technology Transfer Report to Members (Austin, TX: Sematech, 2004); available from Internet:

10. M Bishop, Feasibility Study of the WIS/TIS Module, Sematech Technology Transfer Report to Members (Austin, TX: Sematech, 2002).

11. M Adel et al., “Characterization of Overlay Mark Fidelity,” in Proceedings of SPIE, vol. 5038 (Bellingham, WA: SPIE, 2003), 437–444.

12. WJ Trybula, “Challenges of Image Placement and Overlay at the 90-nm and 65-nm Nodes,” in Proceedings of SPIE, vol. 5038 (Bellingham, WA: SPIE, 2003), 286–292.

13. P Leray, D Laidler, and I Pollentier, “Comparison of Pattern Placement Errors as Measured Using Traditional Overlay Targets and Design Rule Structures,” in Proceedings of SPIE, vol. 5038 (Bellingham, WA: SPIE, 2003), 49–60.

14. JA Allgair and KM Monahan, “Microeconomics of Overlay Control at the 65 nm Technology Node,” in Proceedings of the IEEE International Symposium on Semiconductor Manufacturing (Piscataway, NJ: IEEE, 2003), 103–106.

Benjamin Bunday is the project manager of CD metrology at Sematech/ISMI (Austin, TX). For four years he has led Sematech’s CD-SEM and OCD benchmarking, evaluation, and technology development efforts. Bunday has been the chief author of the AMAG unified CD-SEM and scatterometry specifications and is actively involved with the metrology chapter of the ITRS. He has nine years of industry experience in the areas of CD metrology, lithography, and etch. A member of SPIE and the author or coauthor of more than 30 papers, he received an MS in materials science and engineering from Cornell University in Ithaca, NY. (Bunday can be reached at 512/356-3989 or

Milton Godwin is a consulting engineer for ISMI. He has been in yield engineering and yield management throughout his 27-year career in the semiconductor industry. He has been yield manager at the Fairchild Center of National Semiconductor and managed Sematech sponsorship and testing in the development of the KLA-Tencor AIT. Most recently, he introduced defect control and preemptive elimination methods to the Advanced Mask Technology Center in Dresden, Germany. He received an MS in administration from Pepperdine University in Malibu, CA. (Godwin can be reached at 512/356-3194 or

Pete Lipscomb is the overlay metrology project manager at ISMI. He originally joined Sematech in 1990 as a metrology engineering liaison to assist GCA and SVGL in scanner development projects. He also helped start up AMD Fab 25’s lithography metrology area and then joined KLA-Tencor in field applications engineering. He received a BS in mathematics from Texas State University in San Marcos. (Lipscomb can be reached at 512/356-7131 or

Dilip Patel is an Intel assignee to ISMI, where he manages the consortium’s defect detection and characterization program. In addition, he is a cochairman of the yield enhancement chapter of the ITRS. Patel has held various positions at Intel, primarily in the defect metrology area. He received a BS in mechanical engineering from Sardar Patel University in Vallabh Vidyanagar, India, and an MS in integrated manufacturing systems engineering from North Carolina State University in Raleigh. (Patel can be reached at 512/356-7074 or

Michael Bishop is an associate project engineer for lithography metrology at Sematech. He has been with Sematech for 16 years, working in all aspects of lithography, and was the process and tool owner for overlay metrology for six years. In addition to supporting overlay benchmarking and development, Bishop supports CD-SEM and AFM benchmarking and development. A member of SPIE and the author or coauthor of 36 technical publications, he received a degree in electronic technology from Texas State Technical College in Waco. (Bishop can be reached at 512/356-7121 or

John Allgair, PhD, is a Freescale Semiconductor assignee to Sematech, where he is responsible for coordinating lithography metrology programs to meet the requirements of the ITRS. He has worked in the semiconductor industry for 14 years in a variety of areas, including design, etch, films, lithography, and metrology. Previously Allgair was responsible for parametric and defect metrology technology development and manufacturing implementation at Freescale. He is on the SPIE program committee for metrology and has published papers in several industry journals. He received a PhD in electrical engineering with an emphasis in semiconductor physics and processing from Arizona State University in Tempe. (Allgair can be reached at 512/356-7439 or

Alain C. Diebold, PhD, is a Sematech senior fellow and a fellow of the American Vacuum Society. He is responsible for coordinating all metrology work at Sematech, where he is primarily involved in the development of metrology technology with an emphasis on promoting industry coordination. In addition, Diebold provides technical management of advanced metrology activities at Sematech. He founded and leads the Metrology Council and Analytical Laboratory Managers Working Group of Sematech member companies. He is also a founder and cochair of the U.S. Metrology Technical Working Group for the 2005 ITRS. He received a PhD in chemical physics from Purdue University in West Lafayette, IN. (Diebold can be reached at 512/356-3146 or

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