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INDUSTRY NEWS

Chipworks Corner

Texas Instruments pushes MEMS
envelope with micromirror-based DLP

While there is obvious interest in the leading-edge CMOS processes, Chipworks has analyzed chips across the spectrum. This series of reports will cover as broad a range of technologies as possible. First, we take a look at one of the benchmarks of the MEMS industry segment—Texas Instruments’ digital light processor (DLP) projection device.

TI started developing the DLP MEMS products in 1987. It launched them in 1994, and market acceptance has been growing at an increasing rate. TI announced shipment of the five millionth unit in December 2004, up from three million the previous April. TI seems to have settled on four main markets: rear-projection TVs, and front-projection units for home, business, and cinema.

The DLP system discussed here came out of a Dell 2300MP projector, together with the accompanying DAD1000 and DDP2000 controller ASICs. The MEMS part of the DLP is actually the S1076-7402 XGA digital micromirror device (DMD). It is a 0.7-in.-diagonal spatial light modulator, using a 1024 × 768 array of aluminum micromirrors, fabricated over five-transistor SRAM driver cells. The mirrors are grouped into 48 blocks, each block containing 48 rows of 1024 mirrors.

The drive circuitry is fabricated in a ~0.6-µm CMOS process using p–/p+ epitaxial substrates. The base wafers are fabricated by TI or foundry partner DongbuAnam; Amkor is said to be the packaging house. The device is packaged in a solidly built hermetic glass/metal/
ceramic assembly (brick outhouses come to mind), complete with a substantial heat slug and internal getter strips. A rectangular window on the inside of the glass limits light only to the mirror array. The device uses five layers of metal, three for the CMOS circuitry and two for the MEMS superstructure.

A corner of the die array is shown in Figure 1; the individual mirrors are 12.7 µm square on a 13.7-µm pitch. The purple-dark areas around the edge of the die are metal 3 (M3) and are covered with a thin oxide tuned to give minimum light reflection and used to screen the address circuitry. The dark dot in the center of each mirror is the support post connecting it to the torsion hinge below. Figure 2 is a SEM image of the M5 mirrors, with two mirrors removed (and, unfortunately, some detritus from the removal process).

Figure 1
Figure 2

Figure 3 provides a closer view of the M4 undermirror metal, revealing the torsion hinge oriented diagonally, with the hinge support plates at the top right and lower left corners of the pixel, connected to the M3 underneath. This M3 line is connected to adjacent pixels at the left- and right-hand edges of the pixel, allowing the row of mirrors to be biased. The mirror-address electrodes are on either side of the hinge, again connected to M3.

Figure 3

The M4 hinge layer and M5 mirror layer are both deposited and defined on sacrificial organic layers. Although not apparent in the SEM images, the M3 in the array is also coated with the same thin oxide as the peripheral metal; this “dark metal” is used to prevent stray light from travelling to the screen when the mirrors are switched off. TI claims this feature improves contrast ratios from 800:1 to >1500:1.

The mirror electrodes are connected to the inverter outputs of an SRAM cell sited underneath each mirror. Since more than 12 V are required to tilt the mirrors, the 7.5-V CMOS transistors in the SRAM cell are inadequate. To overcome this, a large bias voltage (up to 28 V) is applied to the mirror bias bus. This, plus the mirror address electrode bias, provides the electrostatic forces needed to tilt the mirrors. Once the mirrors are latched, an opposite mirror bias is also used to force them to release.

The mirrors are latched and unlatched by binary data, and the grey level of each pixel is determined by the duty cycle of the mirror—the greater the percentage of times the mirror is latched into projection position, the brighter the apparent intensity. The mirrors tilt 12° each way to differentiate between the projection path and the dark path for the incident light.

Figure 4 shows a cross section of the DLP structure, revealing the three conventional CMOS metal levels, the thin (~70 nm) M4 torsion layer, and the M5 mirror metal. The aluminum mirror is optimized to have ~90% reflectivity, and the torsion metal is an aluminum/ titanium alloy, presumably tuned to have the right torsion and reliability characteristics. The M5 layer thins quite noticeably on the sidewalls of the contact to the hinge metal, and the M4 vias are etched deeply into M3.

Figure 4

Figure 5, a close-up TEM image of the mirror/hinge contact, clearly
illustrates how thin the hinge is. Despite the thinness, TI claims remarkable reliability. It appears that TI has simplified the structure over the years: the chip examined here shows the mirror directly mounted on the hinge, whereas the company’s publicity shows the mirrors attached to a yoke, attached to a pair of hinges (see Figure 6). This reduction in mass probably allows the announced increase in tilt angle to 12° from 10°, increasing optical efficiency.

Figure 5
Figure 6

The DMD is a remarkable application of MEMS technology. Its digital drive system provides a switching speed that is orders of magnitude faster than competing LCD technology, and the high optical efficiency, contrast ratio, and reliability are superior to both plasma and LCD displays. As a result, TI claims almost 50% of market share in projector sales.—Dick James

This report is the first in a regular series of device-level process analyses, written exclusively for MICRO by Chipworks’ senior technology adviser, Dick James, a 30-year veteran of the semiconductor industry. Chipworks is an Ottawa, Canada–based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. The technical intelligence customers are usually within manufacturing companies, performing product development, or doing strategic marketing or benchmarking studies. The patent intelligence clients are usually patent lawyers or intellectual property groups within manufacturing companies.


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