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Freescale, Photronics team up

Freescale Semiconductor and Photronics have formed an alliance to
investigate the technical and commercial merits of certain resolution-enhancement technologies (RETs). Their joint research will evaluate the various approaches available for 65-nm-and-below optical lithography applications. The collaboration, a three-year commitment that began in 4Q2004, tasks the chipmaker with supplying representative patterns and unique analytical support, wafer imaging, and data analysis, while the mask house provides test reticles and reticle-fabrication details.

The two companies have already tested multiple RET processes, including 6% embedded attenuated phase-shift and complementary phase-shift masks, and chromeless phase lithography. They say that they found little statistical differences between the methods with respect to critical dimension control achieved at the 65-nm node. The researchers did, however, find differences in important metrics associated with specific RET implementations, such as line-edge roughness and 2-D image acuity. Freescale and Photronics are exploring how these differences and other process improvements can be used to extend RET applications.

TSMC megafab approved

The Taiwanese National Science Council has okayed TSMC’s application to build a $7.5 billion megafab in the Central Taiwan Science Park near Taichung, according to published news reports. Construction is slated to start in January 2006 on an 18-hectare site, with production to begin in August 2008. Second- and third-phase construction plans will follow in subsequent years. The factory’s capacity could be as many as 105,000 wafers per month, with chips featuring 65-nm and smaller design geometries. The company will boost capacity at its existing fabs, including two 300-mm facilities, before the megafab is ready for production.

Taiwan 300-mm plant opens

More than 10 years after opening the inaugural 200-mm wafer-making factory in Taiwan, MEMC’s Taisil unit has started operating the first 300-mm wafer-manufacturing plant on the island. The facility, located at the Taisil site in Hsinchu, is targeted to reach a 300-mm production capacity of about 150,000 wafers per month by the end of 2006, depending on market demand. Combined with MEMC’s large-wafer capacity at its Japanese factory, the company says the Taiwanese expansion will bring its total 300-mm capacity to about 350,000 wafers per month by the end of next year.

“As market conditions dictate, we can install sufficient equipment within Taisil to produce approximately 400,000 300-mm wafers per month, without impacting 200-mm wafering capability,” says Nabeel Gareeb, MEMC’s CEO. “This would allow us to achieve a global capacity of approximately 600,000 300-mm wafers per month within the existing MEMC infrastructure.”

CMP center planned

Rohm and Haas Electronic Materials will invest $50 million in a new manufacturing and technology center for its CMP technologies group in the Chunan Science Park near Hsinchu. Expected to be in commercial production by early 2007, the site will include a 45,000-sq-ft polishing-pad production facility, applications lab, and sales and customer support offices. The 20,000-sq-ft tech center will incorporate a comprehensive CMP consumables lab, which will feature full capabilities for 300-mm polishing and post-CMP cleaning and associated metrology, installed in 4000 sq ft of Class 10 through Class 1 cleanrooms. Pad and slurry product analysis tools and instruments will also be part of the lab, as well as slurry blending systems. The company says the facility’s staff should grow to more than 150 by 2010.

DuPont greenlights China site

DuPont Fluoroproducts will build a new nitrogen trifluoride manufacturing facility at its multiproduct complex in Changshu, Jiangsu province, China. The plant will have 450 tons per year of initial capacity for manufacturing and purifying the high-quality-grade Zyron chamber-cleaning and etch gases when production begins in 2007. The company says the fluorine gas factory is part of a larger strategy to double its investment in the region to $1.2 billion by 2010.

Nano initiative scores funds

The SIA’s Nanoelectronics Research Initiative (NRI) has secured $1 million in funding from the National Science Foundation and another $1 million from a consortium of six U.S. chip manufacturers. Administered on behalf of the industrial participants by the Nanoelectronics Research Corp. (NERC), the NRI will investigate—independently and in conjunction with government organizations—novel approaches in emerging areas of electronics as well as spin, phase, and other quantum variables at the nanoscale level. The goals are to accelerate nanoelectronics research in universities and discover new devices that will work with industry-standard CMOS in 2020 and beyond.

The six participants in the NRI consortium are AMD, Freescale, IBM, Intel, Micron, and Texas Instruments. Intel’s Paolo Gargini will chair the governing council which oversees the initiative’s efforts, with TI’s Hans Stork acting as vice chair and representatives from the other four chipmakers also part of the group. IBM’s Hans Coufal, who is also director of NERC (a unit of Semiconductor Research Corp.), will lead the NRI technical program group.

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