Advertiser and

Buyer's Guide
Buyers Guide

Chip Shots blog

Greatest Hits of 2005
Greatest Hits of 2005

Featured Series
Featured Series

Web Sightings

Media Kit

Comments? Suggestions? Send us your feedback.

BEOL Processing

Copper electroplating, CMP challenges grow
more complex at 65-nm node and beyond

The back-end-of-line (BEOL) challenges facing fab teams as they develop and ramp the 65-, 45-, and 32-nm nodes will grow increasingly difficult and problematic with each successive process generation. Two critical areas of concern are copper electroplating and CMP. Can ultraclean plating baths capable of producing uniform, low-impurity, void-free films be developed that will help keep copper resistivity in check? How will on-line chemical metrology and the analysis of copper electroplating evolve and improve? Will future CMP tools minimize dishing and erosion adequately without damaging or degrading the mechanical strength and properties of porous low-k and ultra-low-k dielectric materials? Is electro-chemical-mechanical polishing (ECMP) a legitimate mainstream contender, and if so, when will it be implemented? What kinds of post-CMP cleaning and drying techniques will be best suited to post-65-nm process recipes? These and other questions are addressed by this issue’s Hot Button panel of BEOL experts from the chipmaking and equipment communities.

VARUGHESE MATHEW (principal staff scientist, Advanced Technology and Manufacturing Center, Freescale Semiconductor): Plating and CMP processes constitute a major share of the integration challenges facing copper interconnects. Given yield-driven interactions, it is beneficial to optimize CMP and plating modules together.

Copper capping is gaining more
attention because of electromigration and lifetime improvements.
Varughese Mathew

A major challenge in low-k/copper manufacturability for 130 and 90 nm has been interconnect defect reduction. This is expected to be even more problematic at the 65-nm node and beyond. Potential sources of copper defectivity may include defects within the barrier/seed deposition process, which may lead to extensive voiding in plated films. Voiding can be detrimental, since it may not be immediately detected by in-line parametric testing. However, voids can migrate and coalesce during anneals and subsequent processing steps, resulting in electromigration failures and other reliability issues. Therefore, robust process solutions include optimized annealing, barrier deposition performance, and copper microstructure, all of which have repercussions for subsequent processing.

When feature density varies widely within a die, it is challenging to get uniform plating among dense and isolated features. Optimum bath composition, especially in terms of additives, and appropriate current waveforms may resolve some of these issues. Continuous control of the plating bath without the accumulation of additive by-products is also important.

To mitigate copper resistivity increases at the 45-nm node and beyond, the reduction of in-film impurities will be needed. New-generation plating baths will be required that can produce low-impurity films, since in-film impurities may lead to increased resistivity. Extensive R&D efforts toward developing high-purity plating baths that are capable of producing uniform and void-free films will be needed to achieve that goal.

Traditionally, nonuniform plating and overburden have been major issues facing the CMP process. A more uniform plating process and improved plating chemistry may help to achieve a reduced within-die copper thickness range and lower overburden. For advanced device generations, processes such as ECMP may become more mainstream.

A major challenge confronting CMP in any manufacturing line is achieving selectivity that is compatible with the required process integration. When a diverse product portfolio is run on the same manufacturing line, the CMP process should be flexible enough to adapt to different dielectric stacks. Some integration schemes may necessitate high copper selectivity, while others may require the use of various dielectric materials. Nonuniform removal of dielectric materials may result in unexpected material-property mismatches and possible reliability issues.

Post-CMP cleans are also important for reducing defectivity. Excessive amounts of corrosion inhibitors and other CMP additives remaining on the wafer surface may cause problems in subsequent process steps, such as the selective capping of copper lines using electroless plating. Copper capping is gaining more attention because of electromigration and lifetime improvements. In addition, it may offer interlevel line capacitance benefits.

In the longer term, plating tools and chemicals may need to be developed or modified so that plating can be performed on barrier materials such as ruthenium and tantalum. CMP processes may have to be modified to planarize such films. In addition, these processes may need to be more compatible with porous low-k materials.

CHENTING LIN (marketing manager, ECI Technology): Copper interconnects require a capping layer to prevent oxidation, diffusion into low-k dielectrics, and surface electromigration. Typical dielectric capping layers have very different thermal expansion coefficients than copper, and their interface properties with copper are not favorable. Therefore, to effectively control copper electromigration and stress migration, many R&D groups have reported using cobalt compounds such as CoWP or CoWB to replace dielectric capping layers. Cobalt compounds are typically deposited using electroless processes.

Electroless deposition is selective. In other words, the capping layer is plated only on exposed copper interconnects. Electroless deposition is more complicated than the typical electroplating process and uses many more chemical components. Concentrations of electroless bath components have to be tightly controlled because they determine the resulting film composition and thickness through the deposition rate. Thickness and composition variations directly impact the capping properties and the resistivity of the resulting film.

It has been reported that optical reflective methods can monitor in-deposition film thickness in situ. Such methods assume that the film properties are consistent. However, because film properties typically depend on the solution concentrations, they vary with bath age and other factors. On-line chemical analysis is therefore the preferred method for monitoring electroless deposition processes. The semiconductor industry has been evaluating several techniques, including cyclic voltammetric stripping (CVS), potentiometric titration, and spectroscopy, to monitor the components of electroless baths. Engineering efforts to integrate multiple analytical techniques as well as pH and oxidation-reduction potential probes into an on-line unit to meet streamlined fab requirements have been reported.

Copper electroplating is becoming increasingly difficult as trench and via dimensions shrink with the ever-smaller technology nodes. Hence, new plating solutions are being developed, and plating chemistries are expected to operate within narrower process windows to ensure quality deposition. In that context, on-line chemical metrology is becoming even more indispensable, not only for analyzing the contents of chemical baths during production but also for helping evaluate new chemistries. While CVS remains the standard chemical metrology technique in most leading fabs, the continuing drive to reduce the cost of ownership and minimize waste has prompted fab engineers to evaluate spectroscopy, multivariate analysis, and other techniques that do not require reagents. It has been shown that spectroscopic methods can be used with high precision to analyze plating solutions’ inorganic components, including copper and acid.

To overcome the electroplating difficulties associated with the shrinking trenches and vias in future technology nodes, electroless copper plating is being evaluated to replace two-step seeding and electroplating processes.

J. D. LUTTMER (manager, external interconnect research, silicon technology development, Texas Instruments): Interconnect technologists are facing increasingly difficult challenges as the industry transitions to the 45- and 32-nm nodes. In addition to the challenges associated with the introduction of porous, ultra-low-k dielectric materials, other integration and materials issues will require extraordinary efforts by development teams. The most demanding of these challenges include achieving 3-D critical dimension control, mitigating or eliminating process damage, improving cohesive and adhesive properties of interconnect stack materials and interfaces, reducing electromigration resulting from increased current-density requirements, managing the large increases in copper resistance caused by shrinking interconnect lead dimensions, and advancing lithography and patterning to achieve novel integration techniques and immersion lithography.

Electroless processes...must be
engineered to prevent doping the copper and thus increasing
J. D. Luttmer

Control of the copper line and dielectric dimensions is essential for ensuring that interconnect performance does not decline.

Improvements in etch uniformity are required to minimize line-edge roughness, line/space width uniformity, and trench depth unifor-
mity. Novel or greatly improved CMP processes that minimize dishing and erosion are necessary, but they will become more challenging as the mechanical strength and properties of the stack components degrade with the introduction of porous low-k materials.

Etch and ash processes are known to degrade the electrical and physical properties of the dense low-k dielectrics used in earlier device nodes, process-induced degradation that is exacerbated by the introduction of porosity. Densification, carbon depletion, and the generation of silanol groups within 5 to 25 nm of etched/ashed porous ultra-low-k surfaces have been reported. Attempts to eliminate this damage are examining modified process chemistries and tools, postprocess treatments, and alternate integration schemes involving various hard masks.

Novel cure technologies involving the use of E-beam, ultraviolet, and plasma technologies are leading to improvements in the cohesive and adhesive strength of low-k interlayer dielectric and intermetal dielectric materials and dielectric etch stops. These improvements are particularly important for the porous dielectrics being considered for the 45- and 32-nm nodes. Likewise, novel copper-polishing processes with reduced shear force are being developed.

Selective processes are being investigated to passivate exposed copper surfaces after CMP processing and improve copper-line electromigration performance. The top interface layer, which is the weak link of electromigration, can exacerbate stress-induced voiding. Electroless processes such as cobalt and nickel alloy deposition and thermally driven selective silicidation are being considered, although these approaches must be engineered to prevent doping the copper and thus increasing copper resistivity.

Electron scattering in fine-pitch copper lines will become more important at the 45- and 32-nm nodes, particularly for local interconnects, producing a near-exponential increase in copper resistivity as features sizes diminish. Both the thickness and the width of these local interconnects are approaching the mean free path of electrons in copper. Likewise, impurity and grain-boundary scattering is becoming more important, requiring significant efforts to improve copper-line quality through new chemistries, anneals, and alternative
fill processes. Efforts to increase the relative copper volume in interconnect leads are also driving the need for ultrathin and directly platable metal barriers.

JOHN DUKOVIC (distinguished member of technical staff, thin-films group, Applied Materials): Electrochemical plating (ECP) and CMP are central unit processes in all copper interconnect flows. They are well established and are expected to be extended into the 65-, 45-, and 32-nm logic generations. In both processes, defect performance is critical and has been the focus of much attention, especially during technology-node transitions.

Largely through advances in plating-cell design, much progress has been made toward reducing postplating defects. One such advance has been the separation of the wafer from the anode using a cation-specific membrane and two independent plumbing loops for the catholyte (plating electrolyte) and the anolyte.

Another key advance has been in the motion sequence that is used to immerse the wafer in the electrolyte. The occurrence of wetting-related defects, including dot-line voids and swirl patterns, has been greatly reduced by using “swing immersion,” a mechanical motion sequence in which the wafer is rocked forward and then backward as it is immersed in the plating solution. The ability to eliminate void defects through the mechanical manipulation of surface wetting has removed the need to further complicate the plating chemistry with surfactants and has allowed plating-chemistry advances to be directed toward the more fundamental issues of gap-fill and reliability.

A troublesome post-CMP defect type is the “pull-out” or “missing-metal” defect. The occurrence of this defect depends strongly on post-ECP annealing conditions, and one way to control it is to optimize the anneal temperature and the temperature transients during heating and cooling. While higher anneal temperatures and abrupt heating and cooling transitions are problematic (presumably because they induce higher mechanical stress gradients), lower temperatures and gradual, controlled transients result in significantly lower missing-metal defect counts.

A widely recognized challenge facing CMP is the need to accommodate continually emerging low-k and ultra-low-k dielectric materials, whose low mechanical strength reduces their resistance to mechanical damage. Mechanical damage, including cracked dielectric and lifted copper lines, can be reduced by decreasing downforce during CMP processing, which reduces the frictional shear forces that cause such damage. A process with greatly reduced downforce that also avoids the use of abrasive slurries is ECMP, which removes copper by anodic dissolution while recessed regions are protected by a passivation layer. Because ECMP reduces scratches, fabs can devote more attention to improving dishing and erosion during the barrier-polish step.

Another defectivity concern is the presence of particles and residues that are left on the wafer during post-CMP cleaning and drying. Because dielectric materials with decreasing k-values are increasingly hydrophobic, they are difficult to dry using conventional spin-rinse drying without leaving a copper-containing water-mark residue on the dielectric surface. A solution to this problem is vapor drying, in which the surface-tension gradient in the meniscus prevents the formation of water droplets as the wafer is withdrawn from the isopropyl alcohol–water rinse.

MicroHome | Search | Current Issue | MicroArchives
Buyers Guide | Media Kit

Questions/comments about MICRO Magazine? E-mail us at

© 2007 Tom Cheyney
All rights reserved.