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MicroMagazine.com

INDUSTRY NEWS

Will DFM become the lingua franca of the chip world?

DESIGN FOR MANUFACTURING: With 90-nm processes and below, DFM strategies have taken on a new urgency.

Mike Gianfagna likens chipmaking to building a high-rise. The only problem with the comparison is that the hardhats do a better job with their steel, bricks, and mortar than the bunnysuits with their silicon, chemicals, and gases in one key respect.

“An analogy I like to use is: If commercial construction was done the way chips were built, half of the buildings would fall down,” asserts Gianfagna, the CEO of Aprio Technologies in Santa Clara, CA. The reason? The design and manufacturing sides of the industry have the high-tech equivalent of a Mars-Venus problem.

In the executive’s analogy, the designer is the architect, and the manufacturer is, of course, the construction crew. Sure, the manufacturing guy has a set of “blueprints.” The problem is that in the IC industry, the design engineer is “largely clueless” about the constraints imposed on manufacturing. For example, Gianfagna notes, “The design engineer puts polygons on a layout. Does he have any idea how they look when they’re printed on a wafer? They’re very fuzzy and have irregular shapes. He thinks they’re a regular shape and this is what the circuit is going to look like. In fact, it doesn’t.

“When an architect designs a building, he understands the client’s need for the space, how it needs to work, the aesthetic function, and he is very well aware of shear forces and materials strength. And he [designs] the building to…withstand things like wind and earthquakes,” says Gianfagna, whose company specializes in a design-for-manufacturing (DFM) platform that simplifies how resolution-enhancement techniques (RET) are applied to mask data.

When a construction crew shows up on a job site, “they know what they’re building,” he points out. “When a manufacturing guy gets a design from a designer, he doesn’t know about circuit performance constraints,” to take one example. “You’ve got these two sides who are largely clueless about the other’s constraints.

“The construction crew knows what the load-bearing walls are,” the executive adds.“Those pieces of the building are what holds it up, as opposed to an interior wall or walls for looks only.”

The industry can no longer solve the problem by “coming up with better tools for design and better tools in manufacturing. We have to build an infrastructure that bridges the gap between the design and manufacturing communities. That’s a very challenging problem to solve.”

Working with 250- and 180-nm processes, “you could clean it up after the fact,” says Gianfagna. At 90 nm and 65 nm, life on the process line becomes more difficult. “The problems, or the challenges, of manufacturing have been so great, the designer has to be involved. You can’t clean them up afterward. The designer has to understand that when I put a polygon down, it looks very different in silicon.”

Coming up with a definition of the problem is part of the problem, he explains. “An important metric for any DFM strategy, if a company claims to be solving a DFM problem, is, first, ask their perspective. Are they dealing with issues on both the design and manufacturing sides?” The “huge disconnect” on the manufacturing side arises because, unlike its design counterpart, manufacturing “is not hierarchical and incremental: it’s sequential and flat.”

At Semicon West in July, SEMI sponsored a Fab Managers Forum conference on design for manufacturing that brought together presenters from the design, manufacturing, and equipment segments to discuss these issues. Mark Mason, RET manager at Texas Instruments, told attendees that “DFM is no longer just a nice thing to have. First-pass success is expected.”

“DFM is happening at TI,” said Mason during the panel discussion following the presentations. “I don’t think you can make the argument that we’re not making inroads on this problem. I think the myth is there’s some magic marketing [switch] called ‘DFM’ that you can just turn on. There isn’t. It’s a culture, an infrastructure, a business process, and it’s not a thing you can just go do. It’s a culture and a series of things you have to do, and we’re doing that.”

Panel participant Mike Smayling, CTO of Applied Materials’ Maydan Technology Center, recalled using optical proximity correction (OPC) in 1984 and model-based OPC at Rice University in 1990. “There were complaints about data size even then,” he told attendees. “Well, it’s only gotten worse.”

Applied is working with several industry partners on the X Initiative, an alternative to traditional Manhattan IC architecture. Smayling said that the X layout has shown mask, wafer, and electrical results that are comparable with Manhattan layouts. Customers are now asking for design rules based on X data at Applied, he noted. The company’s OPC Check capability on its Verity SEM metrology tool “is a good example of an effort on both the EDA [electronic design automation] design and equipment side to get design automation into fab equipment and get data from that equipment to the design side.”

Smayling calls DFM “a contact sport. You have to stay in contact closely and systematically.” In a postconference interview, the CTO emphasized the important role of process uniformity in the technology center’s mission. “A large part of manufacturing is: Can you get the same process to all the dies on the wafer? When we do things like the X test chips, we’re not just measuring one site on one side on one wafer and saying, ‘that passes,’ and then writing a paper on it.” Applied is demonstrating that “not only can we do one location, but we can do every location.”

Translating requirements from the design side to the manufacturing side and vice versa can be difficult, Smayling observes. “Both sides have different agendas. The designers want to make their lives more comfortable by designing with tighter criteria, and the process people would like to make their lives easier by relaxing the requirements.”

The “multilingual” nature of this relationship means that “the integration and design folks have to work hard to bridge that gap. It’s hard for us sometimes,” says Smayling. “We try to explain to the design and EDA people why things are important, and they’re looking at it, saying, ‘a wire is a wire, why are you looking at this wire?’ ” On the device side, “we talk to process people and they’re worried about temperature and throughput.”

Manufacturing and design “are two vastly different worlds with different languages” based on different academic backgrounds and focuses, insists Dipu Pramanik, director of DFM solutions for Synopsys, an EDA supplier. It’s an issue he’s confronted for the last 20 years, and trying to bridge those worlds is like switching “from English to Russian,” says Pramanik, who participated in the SEMI forum.

If there’s a critical net in the design that has tight timing tolerances, the manufacturer needs to know that, and he has to process that piece of the circuit differently, he notes. “The challenge is you can’t overwhelm the designer with all this analysis.”

Certainly, communication is the warm and fuzzy byword, but finding the proper method is key. “I think cooperation in the human sense is no problem,” TI’s Mason says. “Every designer wants his design to work. Every manufacturing facility wants to have high yield.”

The question is, “How do we cooperate?” he adds. TI believes that the industry needs to establish frameworks “to communicate information up and down the design flow.” An example could be “a very complicated logarithmic limit to a certain printing process…for a gate pattern that can’t be easily described in a traditional way.”

The designer needs to know at some point in the design flow process whether the concept passes a manufacturability test or not, “and if not, can you help me understand how to fix it? That sort of information has to be encapsulated in these transportable models, essentially computer codes that can move back and forth between manufacturing and design [and] are sometimes encrypted to protect intellectual property.”

The IP issue as a particular DFM bugbear for foundries elicited a variety of responses when it was raised at the SEMI forum. The moderator mentioned the perception that foundries present a “structural problem.” Viewing their operations as a value-added commodity service, foundries are very guarded about sharing proprietary information. Will that inhibit DFM if you have to depend on different design-rule checks all the time?

TI’s Mason doesn’t think so. “Most of the tenets and the coarse parameters for DFM are the same across companies. We’re all using the same exposure tools; we all have the same need for redundant vias, and so on. We have the same CMP tools. We use the same slurries. We’re all dealing with the same supplier base. So if Synopsys, for example, or Mentor Graphics…comes out with a DFM tool and deploys it across the world to every design seat on the planet, then every designer initially has this ability to make …an easily manufacturable design.”

In principle then, IBM, TI, TSMC, “or some foundry in India that doesn’t exist yet can make ICs, because all designs are created equal. One of the ways that foundries now particularly add value is that they have very strong back-end data prep processes that improve DFM. Some of them have DFM rules that are unique to their rule sets.”

Foundries may face a threat to their business framework, Mason acknowledged. “The business model challenge for foundries is that it threatens to commoditize the foundry business completely on the yield side. I can see where there might be some issues with that from [their] perspective.”

Panel member Chris Progler, CTO of Photronics, said another potential challenge for the foundries is historical resistance to the “idea of foundry-portable rules. The market leaders may balk at transferring models around.” Typically, companies trying to establish themselves welcome the idea, he noted.

Nevertheless, “companies are starting to see real value in DFM,” Progler told attendees at the SEMI forum. “As it moves higher up the management chain and gets more visibility, it’ll eventually hit an inflection point where it becomes part of the culture and is widely adopted. I think there’s a lot of good progress going on at many companies in this area. It’s going to be incremental and progressive. There’s not going to be a switch that turns on.”

There’s no DFM switch, but announcements certainly appear almost daily. Photomask Technology 2005, the conference cosponsored by BACUS and SPIE the first week of October, showcased some of the latest developments. Luminescent Technologies, a start-up making its debut at the Monterey, CA, event, presented six papers. The presentations are a testament to “the extremely interesting technology that’s going to change the industry,” asserts David Fried, president and CEO.

Called inverse lithography technology (ILT), the concept is a simpler, noniterative, and more accurate replacement for RET, the 21¼2-year-old company says. As the name implies, ILT begins the process with the assumed wafer result and then solves a series of mathematical equations to find the best mask patterns that fit the desired outcome.

“As the feature sizes shrink from 110 nm down to 90, 60, 45 and below, it becomes really a very tough problem to solve when you’re trying to iterate a mask,” explains Fried, a 15-year veteran of Applied Materials. “These guys iterate and they can only look at very small segments of the design pattern at a time. What often happens is they make what they think is a pattern that will work, and when they actually print the wafer they find there are things like side lobes, which is something that prints on the wafer from the mask that you had no idea would print.”

Fried says a “whole industry has developed within the DFM area to try to ensure that at least the mask they’ve generated will actually print the wafer properly.” ILT “actually looks at the whole wafer. We look at the global interaction and not just the edges.” The first product to deploy ILT—the Explorer—is already being shipped to multiple customers.

In other developments, three major chipmakers announced in September a DFM initiative for common foundry platforms used in 90- and 65-nm processes: IBM, Chartered Semiconductor Manufacturing, and Samsung Electronics. They call for the use of rules, models, and kits that will enable the companies to reach faster-yielding silicon.

Aprio and KLA-Tencor agreed in July to collaborate on developing an integrated advanced mask design inspection and repair tool. The main difference: Instead of making a tool for designers, the partners decided that manufacturers needed it more because they’re the source of most DFM problems. The partners will focus on a DFM transfer method based on the use of models, instead of the rules-based procedure now used, in order to reduce design redundancy and improve yields.

Will chipmakers get onboard for DFM? Ultimately, they have little choice, insisted Rob Shaddock, another participant in the SEMI forum. “One of the drivers that may come from our end of the food chain is just an increasing intolerance for yield- and timescale-related slippages,” said Shaddock, CTO of mobile devices business for Motorola. “We have hundreds of millions of dollars at stake when we do a product launch. Increasingly, our customers… are becoming intolerant of launch delays and want to pass financial penalties down the food chain, and those are just going to keep traveling down the food chain.” This state of affairs “will give us a strong financial incentive to get more DFM built into this process.”

Who will pay for this development? “That’s an interesting problem, isn’t it?” a smiling Shaddock replied. “If it’s traveling all the way down to the end of the food chain, it seems to be the poor chap at the bottom. Sometimes the payment is not necessarily at the time of the problem. Typically, everyone has a degree of tolerance for the problem.”
Tolerance has its limits, of course, and often a Motorola supplier loses business, Shaddock pointed out. In 2002 a supplier doing “hundreds of millions of dollars” of transactions with the business unit ended up doing “next to zero.”

“And that was the result of missed launches,” he noted. “The penalty, if you like, can have a time lag to it, and that eases the financial burden on the industry in the sense that the money is just getting moved around, but if you’re the person that’s losing that money, it really hurts.”

Adds Pramanik: “If you don’t adapt, you die. What we find is that the companies that come to us, and work with us, and try to solve these problems continue to move ahead, and the companies that don’t, disappear.” Synopsys says most of the interest for its EDA products is coming from the United States and Asia. He was surprised, though, on a visit to Bangalore, India, when “all the designers were asking me about DFM for 65-nm design.”

The industry has shown its willingness to open its wallet, Progler said at the July conference. “If you look at lithography equipment, the industry is willing to pay a half a billion to a billion dollars to develop collectively a new lithography tool that guarantees you a new node. Is the industry willing to fund that kind of level of infrastructure to get you to a new node that doesn’t rely on a piece of equipment? It’s difficult to say. The industry will spend big money for proven solutions.”

Aprio’s Gianfagna agrees with the panel participants who see DFM as the language that the industry will be speaking. “If you don’t solve the problems, you’re going to have a billion-dollar fab sitting idle, and the semiconductor industry is going to slow down. The pressures will force the solutions. We can all talk idealistically, but when it comes down to dollars and cents, that’s what the drivers are.”


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