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Reviewing Process Technology Challenges

Materials, Cost, Productivity, and Risk Management Top the List

by Bijan Moslehi

Bijan Moslehi, PhD, is chief technology officer and senior vice president, semiconductor technology research, for The Noblemen Group, a boutique investment banking, strategic advisory, and business development firm. Moslehi has 20 years' experience working in the semiconductor and semiconductor equipment industries. He can be reached at bmoslehi@noblemengroup.com.

Process integration and the introduction of new materials, tools, and processes continue to be major themes as the industry faces the challenges of 65- and 45-nm technologies. The International Technology Roadmap for Semiconductors (ITRS) has identified an impressive list of challenging technologies and needs, encompassing a host of new processes and materials for both back-end-of-line (BEOL) and front-end-of-line (FEOL) process modules. The ITRS also provides other important chipmaking requirements and guidelines in such areas as 300-mm fab and tool automation and productivity, e-manufacturing, yield and defect/contamination control, advanced process control, integrated metrology, and design for manufacturing. In this year-in-review column, I will discuss some of the major current or emerging technology transitions, including the next wave of copper/low-k interconnect technologies, as well as the trends toward introducing new FEOL materials and processes.

To reduce costs and enhance device performance, the industry has focused its resources on BEOL for most of the past decade, primarily for the implementation of the copper/low-k interconnect/dual-damascene technology. This transition, especially the implementation of low-k dielectric materials, has been a monumental challenge as well as a painful and costly experience. Because of a host of difficulties and early failures, the successful introduction of the complete Cu/low-k technology has been pushed out by several nodes from the original ITRS targets. However, a growing number of companies have managed to overcome the complex integration issues and are successfully dealing with many major hurdles.

In the early days of Cu/low k, the industry had to choose between spin-on-dielectric (SOD) and CVD methods and tools, an evaluation made more difficult by the uncertainty and confusion surrounding the multitude of SOD and CVD low-k dielectric materials candidates. But for the phase of the Cu/ low-k transition using nonporous low-k materials for 90 and 65 nm, the CVD technique (based on carbon-doped oxides) became the consensus winner and the technology of choice. One determining factor informing the decision is that the mechanical properties—and thus reliability—of CVD low-k materials are superior to those of SOD.

Some successful process flows do employ a hybrid approach, which incorporates fluorosilicate glass, particularly in the top interconnect layers. Others use an SOD-CVD film stack, combining the lower k-value of SOD films for reduced intralayer capacitance and the strength of CVD films on top of the stack for limiting damage from CMP. In another attempt to tackle various problems of the standard Cu CMP process—including damage due to the lower mechanical strength of the low-k materials—electrochemical mechanical planarization (ECMP) for copper has been introduced. ECMP, based on a combination of electropolishing and reduced-force CMP technologies, significantly lowers the mechanical stresses applied to the wafers and interconnect materials.

The next copper/low-k interconnect phase introduces porous low-k materials, a transition with its own unique integration requirements and difficulties. Possible trouble spots include pore type (open versus closed, connected versus unconnected), optimized and damage-free etch/strip/cleaning processes, sidewall pore sealing, k-value preservation, thermal conductivity, pore-size distribution and uniformity, and metrology. Undesirable process integration effects must also be prevented, such as low-k carbon depletion, dielectric film densification, void formation, and k-value degradation.

Another emerging problem with copper is directly tied to ever-shrinking design rules. With the smaller feature sizes of the sub-100-nm realm, the effective resistivity of Cu lines has actually started to increase significantly, because of electrons scattering from the Cu grain boundaries and the (rough) interfaces surrounding the Cu lines. This unfortunate phenomenon threatens to negate the speed and performance improvements gained from low-k implementation. Proposed solutions include the use of atomic layer deposition (ALD) to create ultrathin, ultrasmooth diffusion barriers; methods for achieving larger copper grains; designing with shorter metal lines; reducing process and critical dimension variations caused by Cu CMP dishing and erosion; and 3-D interconnect schemes. None of these partial fixes, however, fully and fundamentally address the entire problem.

Industry attention has shifted to FEOL processes, with changes under way that will directly affect transistor architecture and design. Leakage, heat, and power have emerged as top technical challenges in the nanoscale regime. With each technology node, the off-state device leakage, the total device active and leakage power consumption, and heat have been exponentially increasing. These interrelated factors foster a rapid degradation of chip performance, shorter battery life, and escalating packaging and cooling costs. If the trend continues, leakage power will exceed active chip power consumption, even when the transistor is in the off-state.

Most FEOL solutions compromise performance significantly and trade it off for lower power. Fundamental innovations must address the various sources of leakage, particularly gate, subthreshold, and junction leakage. Among these mechanisms, subthreshold is perhaps the most difficult to reduce and suppress. These challenges have forced the creation of two process technology paths for high-performance and low-power devices, with each approach designed and optimized to best suit its specific needs and requirements.

Recent approaches have focused on substrate engineering using silicon on insulator (SOI), strained silicon (sSi), and silicon germanium. SOI use has been limited, with implementation mostly in some very high-performance/ high-speed products. To achieve better performance, SOI is transitioning from partially depleted to fully depleted technology. A more attractive approach is sSi, which leads to enhanced electron mobility and thus helps increase transistor drive current and boost device performance. Strained silicon has an economic trade-off, since it is estimated to be about 2% more costly to use.

An emerging process technique for gate-leakage reduction employs high-k gate dielectric/metal-gate electrode technology, which will replace the traditional gate oxide/doped polysilicon-gate stack architecture. Metal-gate electrodes address the issues of poly depletion, boron penetration, and Fermi level pinning effect at the high-k dielectric/polysilicon interface (where the interface charge accumulation would lead to threshold voltage shifts). A fully silicided gate electrode such as doped nickel silicide is one option under consideration for early-stage deployment.

However, the ultimate solution will likely involve a dual-metal-gate electrode, with the work function of each metal optimized for each PMOS and NMOS transistor. This major technology transition was supposed to occur at the 65-nm node but has been significantly delayed. There are indications that it may not even be ready for 45 nm. Consequently, to counter the gate leakage problem at 65 nm, gate-oxide thickness is being increased, leading to significantly lower performance.

ALD had been seen as the most suitable deposition process for the targeted high-k materials—hafnium oxide, hafnium silicate, and hafnium silicate oxynitride. However, alarmed by the ALD platform’s low throughput and high costs, industry leaders have questioned the suitability of high-k ALD for production fabs. They believe that metallorganic CVD will emerge as the method of choice, a view that is progressively getting stronger but is still not shared universally. If this discussion sounds familiar, perhaps it’s because of its eerie resemblance to the SOD versus CVD low-k debate, only this time the argument is over high-k deposition.

Another FEOL trend involves the implementation of increasingly aggressive ultrashallow junctions for reduced leakage, using newly introduced flash-lamp anneal (or possibly laser anneal) tools for better thermal budget control. In addition, nickel silicide (with ~5% platinum added for improved thermal stability) is replacing cobalt salicide.

Each new set of materials and process technologies requires specialized cleaning processes and chemistries, optimized for each masking level. Among the most challenging requirements are damage-free cleans and particle removal at the sensitive and fragile gate level and post-high-dose implant strip and cleans—with negligible film/material loss for both applications. Another tricky area is postvia etch cleans: the process cannot cause any k-value changes for low-k dielectrics with high-aspect ratios.

Once again, even seemingly straightforward technology transitions are fraught with extreme difficulties, high risk, and mushrooming costs, and they will likely face major delays. For the most part, because of their enormous complexities, technology changes tend to gradually evolve a step at a time over an extended period. With the high levels of uncertainties involved, extreme caution must be exercised in managing risks. Premature reliance on or adoption of new technology solutions may prove to be costly, yet late implementation of critical innovations could lead to lost market opportunities. A prudent approach calls for a sound and practical strategy with a strong business perspective, one which properly factors in the timing, maturity, and economics of these transitions based on a thorough analysis of the realistic technology requirements versus actual market needs for products and applications. In addition, technical collaborations through precompetitive alliances and partnerships provide opportunities for cost and risk sharing, while enhancing the chances of successful transitions.


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