Do we really need a bigger wafer?
The end of the calendar year not only signals the Judeo-Christian holiday season, but the publication of the new edition of the International Technology Roadmap for Semiconductors. One roadmap topic likely to stir up heated discussion is the proposed next-wafer-size (NWS) conversion from 300 to 450 mm.
Many observers doubt whether the industry can afford the conversion, while others point to IC history and argue that the industry cannot afford to forgo it for economic reasons. At the recent ISMI Symposium on Manufacturing Effectiveness in Austin, TX, a panel of experts discussed the NWS conversion, among other issues. (Disclaimer: I moderated the panel.) Another voice in the debate appears in the newish SEMI white paper, "Semiconductor Equipment and Materials: Funding the Future," written by Infrastructure's Ron Leckie. With a handful of companies just getting comfortable with 300-mm production and scores of others still employing 200-mm and smaller substrates, the idea of gearing up for another silicon wafer-size expansion has people reeling.
The new ITRS targets 2012 for introducing 450-mm wafers in volume production. Although discussions have begun in earnest, the roadmap also makes clear that efforts must be greatly accelerated. The document's executive summary notes that "migration to the next
diameter wafer has historically been occurring roughly on a 9–11 year cycle.... This means that to meet the newly stated timing, the industry is already several years behind schedule. Furthermore, a number of highly coordinated actions, such as setting standards, need to occur before any actual product/ equipment development can be initiated."
Later, the summary presents a veritable viper's nest of obstacles in the NWS path. The technical issues (silicon on insulator rather than bulk silicon, huge but thin wafers, tricky litho) are more daunting than with 300 mm, while the economic challenges "are arguably more myriad than the technical ones," with costs for developing 450-mm process tools in the range of "several tens of billions [of] dollars, at a minimum." The big question is, who is going to pay for it?
Still smarting from the financial afterburn of the off-again/on-again 300-mm conversion in the 1990s, equipment and materials people are some of the loudest dissenters in the NWS debate. SEMI's white paper details a growing R&D funding discrepancy, with data showing that the tool sector, "even with no increment for next wafer size, is looking at a potential $4.8 billion gap in attempting to meet a $12.4 billion R&D demand by the year 2010." On the materials side, the report says that the gap could grow to $1.4 billion when NWS is factored in. Clearly, the suppliers can't be expected to shoulder the economic burden of equipment and materials R&D without serious assistance from their customers and precompetitive, cost-sharing collaboration that goes well beyond standards activities.
The lone tool guy on the ISMI panel voiced an alternative scenario. Eric Englhardt, Applied Materials' director of automation products, said he has "looked at...in some detail what the world may have looked like if we would have invested the same amount or maybe half as much [as in 300 mm] in improving 200 mm. I've learned we do have options."
While acknowledging the economic benefits gained from the 300-mm conversion, Englhardt stated that "one of the challenges…is to accept this cost-reduction challenge and to look for ways of dramatically improving the efficiency of the factory without this wafer size [conversion]. Maybe we need '300 mm Rev. B,' and we have to invest in redesigning our equipment.... We don't have to
develop different wafers. But that being said," he concluded, "maybe we can't stop it....We have to be prepared for both worlds."
Then again, maybe the industry can stop it. If all sides of the NWS debate are heard and reason prevails, and the biggest chipmakers don't force their agendas on the rest of the community, maybe the brakes can be applied. Wouldn't the industry's scarce resources be better spent on researching and developing more productive and integrated toolsets and factories, next-generation lithography, new materials, and nonclassical and post-CMOS device structures than on the infrastructure required for getting a bigger slice of silicon into production in less than seven years?
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© 2007 Tom Cheyney
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