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IMEC'S Luc Van den hove

IMEC has much to show for its efforts over the past two decades. At its founding in 1984, the Belgian research institute received the bulk of its funding from the government of Flanders, had one associated lab (at Ghent University), and submitted its first patent application. Today, it receives more than 80% of its funding from private sources, maintains relations with universities all over Europe, and holds approximately 50 patents. Twenty years ago, IMEC's staff numbered 70 people; today, nearly 1400 people are on the payroll.

With a 200-mm cleanroom and a 300-mm facility almost up and running, the institute collaborates with more than 500 partners, including dozens of the biggest chipmakers and suppliers on the semiconductor playing field. In October, IMEC announced that Taiwan Semiconductor Manufacturing Co. has joined Infineon, Intel, Matsushita/Panasonic, Philips, Samsung, STMicroelectronics, and Texas Instruments as a core partner in the institute's sub-45-nm research program. In addition, IMEC has initiated a 45-nm analog RF CMOS industrial affiliation program and is part of the Holst Centre, a joint endeavor with the Dutch R&D organization TNO that will concentrate on future-generation wireless autonomous transducer technologies and systems-in-foil.

During the institute's Annual Research Review Meeting on October 1718 in Leuven, Belgium, I spoke with Luc Van den hove, IMEC's vice president for silicon process and device technology. A member of the institute since 1984, Van den hove concentrates on silicon-based process technology, including advanced CMOS technologies and their process modules. In addition, he is responsible for IMEC's 200- and 300-mm silicon pilot lines. The author of more than 100 publications and conference papers, he received a PhD in electrical engineering from the Katholieke Universiteit Leuven.

At the conclusion of our conversation, Van den hove described the decision to build a 300-mm cleanroom: "If anyone had said in 2000 that we should have a 300-mm cleanroom, we would have thought that that was crazy. We'd have to build an entire new cleanroom. The planning for the new facility began in the 2002 time frame. That's when we made the plans and got all the resources together. It's pretty noteworthy that we did that in the midst of the downturn in the semiconductor industry." Such bold moves have helped make IMEC one of the world's premier semiconductor research establishments.—BM

MICRO: From 1996 to 2004, IMEC's pilot line baseline shrank steadily from the 0.35-m to the 65-nm CMOS node on 150- and, later, 200-mm wafers. Then last May, you announced that you opened a nanotechnology research laboratory for the sub-45-nm node-CMOS technology again. Could you tell me about the work of that 45-nm nanoelectronics research laboratory?

Van den hove: The overall activity in this large program is to develop the basic building blocks that are required to set up a 45- and sub-45-nm CMOS technology. In general, we see that in order to stay on the performance curve, with shrinking devices gradually continuing to increase the performance of the devices, we need to insert many new materials, many options, many new technologies. So the purpose of this program is really to assess or investigate the various options that are available, narrow down the technology choices, and then leave it to our partners to make the final selections, depending on their own specifications for the technologies that they want to implement.

MICRO: In mid-2004, you began to install front-end tools in your new 300-mm-compatible cleanroom, and work was expected to continue until the middle of this year. Could you to go into more detail about the work in the 300-mm cleanroom? I know that you've got an FEOL toolset in there now. What are the priorities for the work in that new cleanroom going to be?

Van den hove: We started installing equipment in the middle of last year, and we now have the full front-end-of-line equipment set installed. We produced the first fully functional silicon (45-nm planar and FINFET technology) by July 15, which met our original schedule. We will start installing the back-end tools at the end of this month (October 2005), and we plan to have all tools installed by the end of the first quarter of 2006. That will allow us to have all modules qualified by the middle of 2006.

At the moment, the focal areas within the program are lithography research, where we have a very strong program on immersion lithography, which we will expand to include hyper-NA immersion and EUV lithography beginning in the middle of next year. Then we have a very strong focal point around front-end device architectures, device technology, where we look at the shrinking of planar device transistors. But we also look into new transistor architectures, such as FINFETs. And we have interconnect activities, where the shrinking of copper/low-k is being investigated, but also new technologies, such as 3-D interconnect, 3-D stacking of chips, and so on. And then we have some more-exploratory sorts of activities that deal with germanium/III-V and nanoelectronics activities, such as carbon nanotubes and interconnect nanowires.

Those are the main activities within the program. We have been carrying out those activities in our 200-mm facility, and gradually we are moving over to 300 mm. And as for front-end device research, this is happening as we speak. Thus, we got our first results in the middle of this year, and now we're ramping up more and more activities on the 300-mm side for the front end. For the back end, this will happen in the next two quarters.

MICRO: What are some of IMEC's new programs or recent findings of interest? You have mentioned a number of things, particularly in the front end, such as shrinking planar transistors and FINFETs. What about interconnects? What are some of the findings coming out of the work that you've been doing?

Van den hove: It's difficult to summarize the major research findings in a few sentences because there are so many. The program is very broad, and there are lots of activities in all kinds of fields. So it's hard to kind of take a snapshot. But if, for example, we look at the lithography program, we recently achieved real breakthrough data demonstrating that indeed it is possible to bring the defect density for immersion lithography down to acceptable levels. This was a real breakthrough result in an area—immersion lithography—that many people were very skeptical about and were wondering whether it's ever going to be possible to get defects down to acceptable levels. The recent results have demonstrated that it is possible. So that classifies as an important breakthrough.

In terms of the front-end device architecture, a lot of progress has been made on high-k dielectric, where for low-standby-power applications we do have solutions now that provide the required device specifications. We have also made a lot of progress on hafnium-based silicates in the area of high-k, in combination with fully silicided metal gate technology. These are just a couple of examples.

The end of last year we also demonstrated FINFET technology and fabricated a very small SRAM cell, by which we demonstrated that these FINFETs can actually be used to fabricate real devices. We reported on the smallest SRAM cell ever made with FINFET devices at the IEEE Electron Devices Meeting at the end of 2004.

In the cleaning program, I think our work on Rotagoni drying techniques has also become very well known.

MICRO: I would like to discuss the front-end area. What is the focus of your FEOL work? You have mentioned a few things: planar transistors and FINFETs that seem to be able to develop real devices. How are you approaching strained-silicon challenges such as film choice? High levels of channel strain increase the risks of defects. How is IMEC facing that challenge?

Van den hove: Regarding the front-end device work, your first question was related to the strain in the device. We are investigating several approaches for bringing strain to these devices. I would say that one of the most popular approaches today is the use of a silicon germanium source/drain deposited by selective epi in the source-drain areas, which really enhances the PMOS current. That is a very important approach that has already been proposed by Intel, but it is being pursued by many companies at this time. This is a route we are also pursuing both on planar devices and FINFET technology, where you can apply the same idea, but on the fin. By doing this, you have two advantages: one is that you bring strain into the device, and second you thicken up the source/drain regions, which lowers the source/drain resistance. Our point of focus there is not just trying to repeat what has been published, but rather to combine this with other techniques to see whether the strain can be additive and whether it can improve the performance of the device.

MICRO: What other techniques?

Van den hove: The other techniques we are investigating include the use of compressive layers, or tensile layers, on top of the devices. There are several options for how these layers can be integrated into the devices: you can use two deposition cycles or, through memory effects, you can change the strain in those layers.

Combining that method with metal gates changes the picture, because in the metal gate itself, you have a component of stress. The main research focus in our work is a combination of all these techniques and what the optimal combination is.

That is the focus in our strain-related research. A lot of progress has been made in that area. We now consider this a kind of baseline technology in our strained process flow, so a lot of insight has been gained in that area. The real research is to combine this baseline technology with materials such as gate stacks and other new process modules.

MICRO: What work are you doing with high-k dielectrics, which you have just mentioned, in the prevention of gate leakage?

Van den hove: In terms of high-k, I have already mentioned that we made substantial progress on hafnium silicate-based materials. Especially for achieving low-standby-power specs, we think that processes are available. Most of our work on high-k has been focusing on hafnium-based materials, and those are now at the point where they can be implemented.

In terms of gate materials, we believe that they should be implemented together with the metal gate approach. Another area where we have done a lot of research is on the fully silicided gate, where you create the metal gate by growing a silicide and converting the poly completely in the silicide. We think that's a very convenient, easy way to implement metal gate technology. In combination with hafnium-based silicate, that's turns out to be rather effective.

We believe that down to the 1-nm level, these hafnium-based materials can provide a solution. But it's going to be very hard to push it considerably beyond 1 nm. So that's why we are ramping up activities on alternative high-k dielectrics. There we are far from having a consensus on which materials to go with, so we're investigating a wide range of materials, such as hafnium tantalates or scandates, among others.

MICRO: How about defects and strain?

Van den hove: We believe that if a moderate level of strain is applied, we don't seem to suffer too much from defects. I don't think it's a very critical issue for the stress technologies that I have mentioned. For the approach where biaxial stress is introduced by the use of thick strain relaxed buffer layers (SRB), we have seen many defect issues. That is why we have abandoned this approach.

MICRO: There seems to be controversy about whether atomic layer deposition (ALD) is the way to go. It's considered not to have very good throughput and to be fairly expensive. Some people are proposing that a metalorganic chemical vapor deposition (MOCVD) approach may be an alternative to ALD. Do you think that ALD is controversial?

Van den hove: I fully agree with the statement that there is a lot of debate about ALD at this moment. I would say that for the first generation of high-k materials—hafnium silicates or nitrided hafnium silicates—we get similar results with MOCVD and ALD. It's hard to discriminate. For layers up to now, such as hafnium-based silicates in the 1- to 1.5-nm region, we don't see a real difference between ALD and MOCVD. I think both techniques can provide films of high quality.

ALD does have the potential that for very thin films, it is intrinsically possible to exercise control atomic layer by atomic layer. There is a potential to go to graded layers and to have better layer control. So we are very strong proponents of ALD. I believe that it's a very important technology. Yes, the throughput is lower, and so quite a few people are worried about that. You can always compensate for that. There are design concepts in which you have multiple wafer deposition at the same time. Therefore, we believe that throughput can be addressed by optimizing the configuration of the deposition tool to a small batch-type system. Also, in the end, the layers are going to be thinner and thinner, and therefore the throughput may become acceptable. Today, we don't think ALD is absolutely needed, but for future films, we think it provides real potential advantages.

MICRO: What are the cleaning challenges at the front end? How is IMEC handling resist removal, high-k dielectric cleaning, and selectivity issues?

Van den hove: I think that the cleaning challenges to a large extent remain the same as before, only that the requirements, such as particle dimensions and the like, continuously get tougher as dimensions decrease. In that sense, the drying of wafers is still very critical—not leaving water marks and the like. In general, organic contamination is certainly a worry; we need to pay attention to the removal of organic contamination. This has become equally important.

One area for which cleaning expertise is being used quite extensively these days is immersion lithography. There is a strong link now with the lithography community, because what you are doing now in lithography is putting water on top of the wafer, and so all the problems related to how to dry a wafer, how to avoid water marks, are now very valid for lithography too. What we've done here at IMEC is that we have brought our cleaning people very close to the lithography people, and they are working together in one team to address these critical issues in the lithography area.

MICRO: Drying a part of a wafer that's already been scanned can lead to water evaporation and heat dissipation from the wafer surface, which can cause water spots.

Van den hove: The heat dissipation can also influence overlay performance. Adding water to the lithography process may sound easy. It's an inert liquid. But in reality, it complicates the method quite a bit, and that's where I think from fab people, where we have a lot of experience with cleaning, there is a lot of added value that we can deliver to the lithography community.

MICRO: I want to ask you a question about design, or more specifically, design for manufacturing (DFM). A statement in your 2004 annual report says: "IMEC is aware of the physical gap that exists between process technology, circuit design, and system design. The closing of this gap is a very urgent challenge for industry worldwide and as such a key issue for IMEC." How do you view that? What kinds of work are you doing in this area to integrate the design with the manufacturing?

Van den hove: This is indeed becoming more and more a very important topic. Although we have not set up a very large program with the specific goal of addressing this problem, we are aiding existing programs where you have a stronger and stronger focus to make the bridge to the design community. And this happens at many levels. For example, in the lithography program, there are a lot of activities that you could classify under DFM. We're talking about where the lithography people interact with the designers to come up with design styles that are more lithography-friendly. Also, resolution enhancement technology is being done by a group that interacts a lot with the designers.

The other aspect, the other extreme, is that in our interconnect program we investigate how to address the global interconnect challenge. There we have joint teams with system architects who are thinking about and working on techniques to address the interconnect problem more at the global system level and how to reorganize system architecture to take that into account.

Other topics are issues related to variability. Variability can be introduced because of large variations in processes, because of critical dimension control variations, also the influence of strain on devices, where layout dependencies may introduce different strain levels and therefore introduce more variability. So there our current effort is mainly focusing on characterizing the magnitude of the problem, and then in the second stage well be working with electronic design automation (EDA) suppliers on how to be able to live with this problem.

MICRO: Do you have any relations or partnerships with design companies, or do you plan to?

Van den hove: There are lots of discussions with those suppliers, but we have no formal large partnership that we can announce, except for the lithography activities. When I was talking about the lithography-DFM interaction, there we have several partnerships with the typical EDA software providers such as Synopsys and Mentor Graphics.

MICRO: Earlier, you touched on the question of nanotechnology. What does IMEC's work in the area of carbon nanotubes and nanowires look like?

Van den hove: The focus of what we are doing is not so much to try to reproduce what has been done at many universities, because there are many groups working on these topics at many universities. The focus of our work is not really to demonstrate a device with one carbon nanotube or the like, but rather we try to look at what is available in the university research groups and try to translate that and try to demonstrate some of those techniques in equipment or with techniques that are compatible with the silicon manufacturing area. Or maybe we'll use an initial lithography technique to create a regular structure and then try to grow nanodevices in this regular structure. We think that is the challenge that we have to address.

In any case, we believe that those kinds of approaches are still pretty far out. So it is a smaller activity at IMEC at the moment. About 10 to 15 people, I would say, are working on this. The bulk of our activity focuses on techniques that will be used for the 32- and 22-nm generations, and as an intermediate phase, we believe that beyond silicon, there will also be substantial activities focusing on germanium and III-V materials—again, for devices on top of silicon. We believe that those can be combined with silicon. We see that as a transition toward possible nanotechnology-type devices.

MICRO: You mentioned the universities—you don't want to duplicate their work, but you have relations with many of them. I was hoping you can give me some specifics about which ones you work with. You mentioned the nanotechnology area. What about other areas in which you work together with universities?

Van den hove: In terms of university interactions, we have a great many interactions with the local university here [Katholieke Universiteit Leuven]. We grew out of this university here in Leuven, so we know those people the best. That means that we are working together with many faculties here, with specific departments: the chemistry department, the physics department, the electrical engineering department.

In many cases, the subjects are wide-ranging. For example, in the cleaning program, we work together with the chemistry department; for the very fundamental characterization of high-k materials, we work with the physics department, where they do fundamental measurements on those high-k materials, such as electron spin resonance measurements; also with the materials department. In terms of circuit design and radio frequency (RF) studies, RF CMOS and the like, we have a lot of interaction with the electronic engineering department, where they have more ability to perform very-high-frequency measurements.

For several other programs—especially in the area of very advanced high-k, the area of III-V and germanium, and also the nanotechnology area—we work with many universities. Some work is focused on the European universities—of course we have that opportunity: for example, in the area of high-k, we work with universities in Germany, the UK, Italy, and elsewhere. We also work with a group in Greece under Professor A. Dimoulas [from the Institute of Materials Science, National Center for Scientific Research Demokritos (Athens)].

MICRO: What about American universities, such as UC Berkeley or Stanford?

Van den hove: We don't have formal agreements with those large universities. But we know the people there very well. There are lots of informal contacts.

MICRO: What about funding? I'm familiar with IMEC's funding from the Flemish government and I know that you have relations with the European Commission. How does that compare with government funding levels in other countries?

Van den hove: When IMEC started, we received a very large fraction of our budget from the local government. When we started, it was on the order of 60% government funding, 40% we had to get through contracting. Essentially that was our target. And we very quickly reached that target of 40% industry funding, 60% government. The agreement that we had with our government was that if we wanted to realize further growth, we had to realize it through an increase in industry funding—direct contracting R&D. Basically, our growth has been realized entirely through that. As a result, today, for the 2005 budget, government funding amounts to only 17.5%. The remaining part we get through contract R&D, of which around 5% comes from the European Commission. So that means the remainder has to come from company R&D.

We're quite proud of these numbers because, although we strongly appreciate the help from our government, the money you have to get through direct funding from companies is money you really have to earn in a very competitive environment, and you have to perform year after year to renew those contracts. We're quite proud that we have been able to realize our growth entirely through that channel.

It is difficult for me to compare that with other regions, because I don't know the numbers of the other organizations that well. But I have the strong impression, for example, that New York state is investing a tremendous amount of money in the Albany NanoTech center. The ratio there is completely different from our ratio-the ratio between government funding and private investment.

MICRO: What is your relationship with Albany or Sematech? Are you a competitor or a collaborator?

Van den hove: Let's talk about Sematech first. I think that with Sematech, we had lots of collaboration. We had several joint programs, in fact. Some time ago, at IMEC we even had programs in which Sematech was a formal partner. In recent years, I think that our activities and Sematech's activities have become more and more complementary. Whereas the emphasis of the research at IMEC is really on process and device R&D, Sematech concentrates much more on infrastructure R&D, making sure that the infrastructure is available for the industry.

A couple of examples: In our program we concentrate more on lithography process research; for example, in our immersion program, we concentrate more on demonstrating lithography capability, such as researching resists on a full-field scanner, making them compatible with immersion, demonstrating their defect performance. In contrast, at Sematech, they concentrate much more on infrastructure topics such as making sure that there are masks available to do lithography, investigating materials such as resists earlier, and so forth. They are more likely to do their work on a small-field tool to set up the infrastructure. And once good results have been achieved, we will test them on a large-field scanner.

Many of our partners are driving in that direction. They don't want to pay twice for the same kind of work, so they make sure that what we do is pretty complementary.

About Albany, I think it's a little early to say because Albany is just starting out. They are building out their cleanroom. We have had active programs for more than 20 years. So I think it's a little too early to give examples of such complementariness. But I'm pretty sure that in the future we will also see more and more complementariness.

Overall, there are so many research challenges, and it's going to increase even further. It's unthinkable, or it's not realistic, to think that all research will be done in one place in the world. So we need several research organizations, each of which has sufficient critical mass. It's good to have research activities in Europe, in the United States, and in Japan. I think that some competitiveness between the organizations may not be bad, but it also has to be at the level of cooperation and knowing the people. I think that with Sematech, we certainly have reached that level, and we are certainly very interested and open to a similar partnership with Albany.

MICRO: What do you think are the most difficult challenges facing IMEC or the semiconductor industry as a whole? And what are you doing to address those challenges?

Van den hove: I think that the most important challenge is to anticipate how far the scaling roadmap is going to continue, to demonstrate how long we will be able to drive costs down through scaling and then find the right approaches to widen the activities into the areas of new applications—the biotechnology or ambient intelligence fields. We must make sure that we have all the technology components available to address those potential new fields and markets.

MICRO: You're referring to CMOS scaling?

Van den hove: CMOS scaling, but we must anticipate sufficiently in advance when we will seek the widening of the scope of these areas, making sure the technology is available on time.

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