‘Technology node’ retired
as feature-scaling gauge
ILLUSTRATION BY DIGITAL VISION
Microprocessors and flash devices have knocked DRAM from the driver’s seat in the International Technology Roadmap for Semiconductors (ITRS). MPU and flash technologies approach and often surpass the smallest feature sizes on DRAMs, which historically determined the introduction of next-generation devices. The advancements have prompted the authors of the just-released 2005 edition to retire the term technology node as a measure of feature scaling.
The new ITRS—the fourth completely revised edition—notes that previous iterations used the term to indicate the industry’s overall progress in scaling, defined as “the smallest half-pitch of contacted metal lines on any product.” Today, however, the DRAM is no longer the sole pacesetter.
“We are now in an era in which there are multiple significant drivers of scaling and believe that it would be misleading to continue with a single highlighted driver,” states the roadmap’s introduction.
Advancements in half-pitch as well as in design factors in flash-memory cells have helped to speed up functional density, the document says by way of example. “Flash technology has also advanced the application of electrical doubling of density of bits, enabling increased functional density independent of lithography half-pitch drivers.”
Likewise, the gate-length isolated feature size that drives the speed performance of MPUs and ASICs “requires the use of leading-edge lithography and also additional etch technology to create the final physical dimension.”
The 2005 ITRS edition contains specific references to each distinct scaling feature, but the expectation now is that different device parameters will scale at different rates, with many of those rates tied to specific products. DRAM metal-1 half-pitch still remains at the top of many tables, but the placement “is no longer described as the measure of ‘technology node.’ It is just one among several historical indicators of IC scaling.”
A second major change in the roadmap is a separate chapter for emerging research devices, broken out from the process integration, devices, and structures (PIDS) chapter of previous editions. The change reflects increased interest in nanoscale devices as alternatives to CMOS products as the industry addresses what the roadmap calls “the theoretical limits of CMOS scaling.”
The document emphasizes that CMOS-based devices will remain “the industry workhorse” beyond 2020, although it also states that new devices appearing toward the end of the next decade will use new methods of processing and storing information. Because most of these products will require new materials, a subchapter was added in a new separate section covering emerging devices.
As always, the roadmap attempts to define the technological targets and timelines that the semiconductor industry must meet in order to satisfy Moore’s Law. In that regard, the International Roadmap Committee (IRC) notes that the document has always been less of a forecasting tool than a guide to the direction that industry research should take. The international team that oversees overall roadmap technology characteristics has updated high-level challenges in order to set common reference points.
As a prime example, the 2005 edition tackles an issue that has become the industry’s elephant in the cleanroom: the year that 450-mm wafers will go into volume production. Established as 2012, the date is based on an economics model, the authors say. However, they emphasize that the date is more of a spur to shape the working groups’ focus on the technical issues needed for the transition than it is a precise forecast.
With the term technology node unable to clearly define industry trends, the roadmap notes that scaling varies by device type. Flash-device scaling is on a two-year cycle until 2007, while MPU scaling is on a 2½-year cycle until 2010. As it was in the 2003 edition, DRAM scaling remains on a three-year cycle.
The so-called grand challenges in the 2005 edition are classified into two categories—performance enhancement and cost-effective manufacturing—and separated by year into near- and long-term sections. The near-term years cover 2005 through 2013, and the long-term years cover 2014 through 2020.
A roundup of some key front-end concerns reveals the following near-term challenges:
• Scaling of planar bulk CMOS faces significant problems. High-channel doping required to control short-channel effects “degrades carrier mobility, lowers the drain current, and increases the band-to-band tunneling across the junction and gate-induced drain leakage.” Manufacturing of new ultrathin structures such as fully depleted silicon-on-insulator (SOI) and multigate MOSFETs is on the horizon. However, controlling the thickness of ultrathin MOSFETs such as FINFETs will prove daunting.
• Smaller and smaller cell area for memory capacitors will be needed in order to continue DRAM scaling. The introduction of high-k dielectric materials such as aluminum oxide and tantalum oxide as well as 3-D memory structures will help in this regard. But further scaling will require the industry to use thinner dielectric film or material with a higher dielectric constant, or both, in order to fix process construction.
• Controlling defects such as bubbles and improving photoresists and topcoats are urgently needed in order to make immersion technology the successor to dry ArF lithography. The technology has the potential to extend optical lithography to at least 32-nm half-pitch in volume production. However, with the proposed linewidths smaller than those used in traditional lithography, resists must meet tougher performance standards in immersion for requirements such as line-edge roughness, SEM-induced critical dimension (CD) changes, and defect size. For 32-nm half-pitch wet lithography to succeed, immersion liquids and resists must have a very high index of refraction, and high-index lens materials must be developed.
• Fabs have to introduce new capabilities for factory integration faster and more cost-effectively than before. Diversified customers’ needs on system-on-chip (SoC) devices are fueling a strong demand for a production model combining high-mix and low-volume manufacturing.
• Improvements are needed in the trade-off between manufacturing costs and cycle time. As process rules tighten, the industry must revise task-sharing efforts based on an equipment-engineering system scheme.
• The need to detect increasingly smaller defects to keep pace with shrinking features conflicts with concurrent cost of ownership (CoO) demands for high inspection throughput. The conflict “increases the challenge to find small yield-relevant defects under a vast amount of nuisance and false defects,” the roadmap states. The conflicting requirements hinder the efforts to improve the signal-to-noise ratio.
• Metrology must be chosen carefully and sampling should be statistically optimized to ensure process control based on CoO. Tight process control and high throughput are making in situ and in-line metrology mandatory.
• Device manufacturers will need nondestructive and high-resolution wafer and photomask microscopy for measuring CDs and detecting defects in 3-D structures. Understanding the relationship between the physical object and the waveform analyzed by the instrument can improve CD measurement.
Mirroring the grand departures in the overall roadmap, the 2005 ITRS carries equally weighty changes in several key process areas. In the metrology area, the measurement gurus will be tested by the introduction of new materials, structures, and processes. The experts believe CD-SEM and scatterometry CD measurements can be extended to 32-nm processes for the first time.
One of the major changes is the realization that new transistor structures will require better measurement capabilities, says Alain Diebold, chairman of the metrology working group and a senior fellow at Sematech.
In the past, the industry could say that it’s difficult to know how to measure new transistors “when they’re not well defined,” Diebold notes. In the 2005 edition, FINFETs and similar devices have become more accepted as being typical of the structure of future devices. As a result, “it’s more certain the measurements of sidewalls is an unmet need.”
Diebold also points out that 3-D interconnect had been undefined in the long term. “That’s untrue for the middle term. We now know we’re going to have to do something for 3-D interconnect. We’re looking for an industry-usable 3-D interconnect architecture. That would be important. It’s true that more knowledge is coming around than before.”
Looking further into the roadmap’s future, the working-group chairman believes that nanodimensions “may end up helping us more than we realize to measure things. It may be that the unusual properties of nanodimensions will give us signatures in those materials’ properties that are useful.”
Metrology tool suppliers will be challenged by metal gate thicknesses, Diebold believes. Measuring film thickness in metal gates using optical methods is “a pain right now.” The more stable the process, the easier the measurement, he says. One inconsistent substance is porous low-k material, which many consider to be unstable.
The material properties will cause problems, Diebold explains, because “as soon as you change material properties at all, you have to come up with new recipes. It turns out that these properties seem to be thickness-dependent for the metal films. That’s causing lots of problems right now.”
Regarding particle detection, the industry is most interested in unpatterned wafer measurements for starting materials, notes Diebold. The challenge continues to center on detecting small particles on very smooth wafers. An additional concern is that wafer suppliers “always feel they’re a little bit behind the times” in meeting roadmap needs. Diebold also points out that SOI “creates that extra optical reflection that results in more measurement noise that makes it harder to see small particles.”
The introduction of 450-mm wafers looms large in suppliers’ view of things as well, particularly when they feel “challenged by the need to keep up with all the other technical innovations.”
For yield enhancement, the adoption of 2012 for the introduction of 450-mm wafers will have the greatest impact on defect detection and characterization, says Andreas Nutsch, a working-group participant and member of the Fraunhofer Institute in Germany, and several coparticipants. Wafer size will impact the throughput of defect inspection tools and CoO as investment increases, according to Nutsch and working-group colleagues Andreas Neuber of M+W Zander and Kevin Pate of Intel. The ITRS already recommends maintaining inspection CoO by asking equipment manufacturers to improve their tools using a constant formula expressed in units of U.S. dollars per square centimeter, they note.
The larger wafer size will also affect yield models and defect budgets. However, the working-group colleagues say the impact is difficult to predict because little is known about the fab structure and manufacturing equipment that will be required for 450 mm.
For wafer environment contamination control, the use of 450-mm wafers will lead to more single-wafer processing. This change may affect chemical usage and liquid-chemical purity requirements, the working group says, because future fabs may be able to reduce cleaning processes.
The yield enhancement group achieved at least two important goals in the full roadmap update, according to Nutsch and Ines Thurner, a colleague who works at Infineon. For defect detection, the major achievement was the introduction of the bevel inspection requirement in time to offer guidance for tool development. The introduction of common edge exclusion was an urgent need for the entire ITRS, they note. The process began two years ago, and it was discussed in detail with other technology working groups. Since the topic cuts across the various working groups, additional discussions will continue.
In the new ITRS, the yield group determined that the two top challenges on the industry’s list of priorities are high-throughput logic diagnosis capability and the detection of multiple killer defects. Dirk de Vries of Philips says that patterning challenges in current and future technologies, where optical proximity correction (OPC) models can take several iterations to reach maturity, are leading to increased systematic yield loss on irregular features. In order to expedite the learning process, “it is crucial to have fast localization of defects on sensitive layout configurations in logic. It is also very important to act on as many systematic yield-loss mechanisms in parallel as possible. Logic diagnosis tools provide reliable detection and classification of such mechanisms.”
In the front-end process (FEP) area, much of the discussion centered on the 450-mm wafer introduction, says Carl Osburn, cochairman of the FEP working group and director of advanced electronic materials processing at North Carolina State University. In earlier versions of the document, the prospect of contending with the larger substrate “was far enough out that people didn’t pay enough attention to it.” Now that the introduction is “glaringly near enough,” the industry is realizing that it’s later than people think.
Osburn ranks the relaxation of the CD tolerance on physical gate length also “fairly high up the list of significance. The tolerance previously was plus-or-minus 10%. That has been raised to 12%.” A survey of manufacturers concluded that no one could meet the lower tolerance number, according to the cochairman.
“Everybody would like to see that [10%] tolerance, but nobody can meet it,” Osburn says. “That resulted in red values [indicating no known solutions] right at the outset. So we tried to be a little more realistic and said that although people would like 10%, they’re not doing it.”
Another change in the 2005 ITRS, Osburn says, is a “slight repartition between lithography and trimming.” Although the final gate length stays the same as it was in the 2003 roadmap, the printed feature size is larger, or relaxed, while the amount of trim is increased. As a result, “trim gets a little higher percentage of the overall tolerance budget.”
He adds there’s a “second shoe” that may drop on this issue because “manufacturers do not seem to be keeping up with the gate length numbers in the roadmap, so they need to be reviewed in the near future. And even the increase to 12% CD tolerance is inadequate from the lithography and etch point of view.”
A third area to note is that the need for high-k materials was pushed out to 2008, Osburn says. He explains that this “is mostly a realization that people have until then,” adding that “it would be unrealistic to call it a requirement when nobody is going to use it.” The industry is still waiting for the first company to introduce high-k, “and I think there’s an element of nobody wanting to be first.”
In a document that jettisoned one of the cornerstones of the industry’s development, one of the forward-looking aspects of the 2005 ITRS is the addition of a new section on emerging research materials. The working group for emerging research devices points out that the industry will require new chemicals, synthesis techniques, and metrologies.
C. Michael Garner, chairman of the emerging research materials working group and program manager of materials research at Intel in Santa Clara, CA, says the first synthesis challenge is the control of 1-D nanomaterial structures, properties, location, and orientation.
“Most of the techniques to grow these 1-D structures [nanotubes and nanowires] require a catalyst that initiates and controls their growth and structure,” Garner explains. “We need a better understanding of how the nanostructure and composition of the catalyst interacts with CVD growth conditions to control the resulting nanostructure and composition of the 1-D material.”
Waxing philosophical, Osburn muses that the “crystal ball always turns dark or cloudy two generations from where you are today. People have always said it’s all over in five years; nothing is going to happen. People take somewhat casually the fact that there are a lot of red-brick walls. Having said that, increasingly the limitations are more fundamentally physics than they are technological. And for that reason, for the reds, many of them are deeper reds today than they used to be.”—JC
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© 2007 Tom Cheyney
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