Advertiser and

Buyer's Guide
Buyers Guide

Chip Shots blog

Greatest Hits of 2005
Greatest Hits of 2005

Featured Series
Featured Series

Web Sightings

Media Kit

Comments? Suggestions? Send us your feedback.


Accelerating flash product inspections using a novel E-beam inspection method

David M. Price, Garrett Long, and Doron Gal, KLA-Tencor;
and Laura Pressley and Mike Meyer, Spansion

In the last few years, flash memory has emerged as the fastest growing segment in the memory market. NOR random-access flash is used in high-performance applications such as networking, cell phones, and games. NAND sequential-access flash is used primarily in mass-storage applications, such as digital cameras, personal digital assistants, and other products requiring memory cards. As consumers continue to demand innovative, small, fast, cheap products, flash memory fills the need for low-cost, low-voltage memory with reasonably fast read-write times.

As the largest company devoted to flash memory products, Spansion is under strong economic pressure to ramp its new products quickly, attain high yields, and achieve a fast time to market—all at the lowest cost possible. Part of the company’s strategy is to detect and eliminate yield-critical front-end-of-line (FEOL) defects as quickly as possible during product development and ramp and then to monitor defect levels in production to ensure that yield excursions are detected early.

In production, achieving low costs means monitoring defects using a high-throughput inspection system that can capture defects of interest (DOIs). While optical inspection systems normally perform cost-effective line monitoring, they do not easily detect some critical FEOL defect types. Very small physical defects, buried physical defects, and electrical defects can be detected only by using E-beam inspection.

When end-of-line testing at Spansion’s Fab 25 in Austin, TX, encountered a yield excursion that the optical inspectors had failed to detect, a team of engineers began to investigate the problem using E-beam inspection. While the engineers were able to find the defects, which proved to be cobalt silicide (CoxSiy) fibers less than 20-nm in diameter that had shorted two CoxSiy word lines, scan times took a few hours because a small pixel size was required. It was clear that ordinary E-beam inspection was ineffective because it would significantly limit wafer-level sampling. Hence, an alternative approach was required.

The team recognized that the structure of the CoxSiy layer in which the fiber defects occurred mimics that of test structures from µLoop, a noncontact electrical defect monitoring method from KLA-Tencor (San Jose). Developed a few years ago, µLoop uses specially designed test structures together with E-beam inspection to perform in-line electrical tests. All defects detected by the method are necessarily yield-limiting, and because it detects defects’ electrical properties rather than their physical properties, a large pixel size can be used, greatly reducing inspection times.

Because FEOL floating gate word line structures on flash memory products are similar to µLoop test structures, that methodology can be applied without having to manufacture special test structures. Using the method on product wafers enabled Fab 25 to detect killer defects in approximately an hour per wafer, increasing throughput dramatically. That accomplishment greatly accelerated the learning cycle, allowing Spansion to trace the sources of the defects quickly and alter the process to optimize sort yields.

The Electrical Defect Monitoring Method

The µLoop electrical defect monitoring method uses a specialized test structure together with an E-beam inspection system. The typical test structure illustrated in Figure 1 shows a comb pattern with a set of lines tied together and grounded and an alternate set of lines that are floating and discrete. Electrical defects that occur in comb structures such as opens or shorts create a strong electrical signal during E-beam inspection. The defect monitoring method takes advantage of that signal so that only a portion of the structure must be inspected to locate defects.

Figure 1: Schematic diagram showing the principle behind the µLoop method. The diagram shows the comb-type structures and an electrical short and open. (Graphic courtesy of A Shimada, “Application of µLoop Method to Killer Defect Detection and In-line Monitoring for FEOL Process of 90 nm-Node Logic Device,” IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, Boston, May 4–6, 2004.)

The method performs two separate scans to fully characterize defect density. The first scan, called the assess scan, is used to determine the locations of electrical defects in the x dimension—in other words, the lines on which the defects lie. The assess scan can also be used to estimate electrical defect density. The second scan is used to locate the defects in the y dimension. Called the identification (ID) scan, it is made at right angles to the first scan along each line identified as having a defect. After the defect coordinates have been determined, E-beam inspection is used to generate detailed images of the defects for classification and prioritization. At Fab 25, an eS31 E-beam tool from KLA-Tencor was used.

Since Spansion’s floating gate word line structures have layouts that mimic standard µLoop test structures, the use of the electrical defect monitoring method on product wafers followed the same inspection routine as that performed on test structures. As shown in Figure 2, an assess scan (a) was performed followed by an ID scan (b), which detected killer electrical defects only.

Figure 2: Two types of scans performed in the µLoop method: (a) CoxSiy assess scan and (b) CoxSiy ID scan.

Applying the Defect Monitoring Method to a CoxSiy Excursion

During routine electrical testing of 110-nm NOR flash product, Fab 25 discovered a yield excursion in the CoxSiy layer of the floating gate word line structures. A scanning electron microscope image of the defect is shown in Figure 3. The culprit, illustrated in the schematic cross section in Figure 4, proved to be a CoxSiy fiber defect that bridged the CoxSiy word lines and caused a direct electrical short. The defect was difficult to detect using optical inspectors for two reasons: First, its composition and, therefore, its optical properties are very similar to those of the CoxSiy lines on which it lies, and second, it had a diameter of <20 nm. While fab personnel were able to detect the defects using traditional E-beam inspection with a pixel size of 100 nm, that method proved time-consuming and detected many artifacts associated with the shorting effects of the CoxSiy fiber defect.

Figure 3: Top down SEM image of a killer CoxSiy fiber defect on top of a CoxSiy word line and active floating gate memory device features.
Figure 4: Schematic cross section of typical floating gate flash memory FEOL word line structures and a CoxSiy fiber killer defect bridging the CoxSiy word lines. This defect would cause a direct electrical short.

In order to reduce the inspection time dramatically and focus on the killer CoxSiy fiber defects, a joint task force of Spansion and KLA-Tencor engineers was formed. The breakthrough came when the engineers recognized that the word line structures have a similar geometry to the alternating pattern of grounded and floating lines that comprise µLoop test structures. Hence, they decided to perform an experiment in which µLoop methodology was applied to the CoxSiy layer on product wafers.

The electrical defect monitoring method can differentiate between DOIs—in this case, CoxSiy fiber defects—and artifacts caused by associated shorting. That ability resulted in the elimination of non-DOI defects. In contrast, a standard E-beam inspection tool captured 297 artifacts. By ignoring the non-DOI defects, the new method realized substantial inspection time and tool throughput improvements. Inspection times were reduced by more than 50%, while tool throughput increased by 71%.

Based on those results, Spansion became interested in deploying µLoop on the production floor. To that end, the team began testing the method on the CoxSiy layer of multiple production wafers. The application was set up in the same manner as a µLoop test chip, and initial inspection results were fast and accurate.

Figures 5a and 5b compare wafer maps of the CoxSiy process layer generated during standard E-beam inspection and µLoop inspection, respectively. The standard E-beam scan captured 304 total clustered and nonclustered defects, only seven of which were identified as CoxSiy fibers, while the µLoop scan captured only seven defects, all of which were found to be CoxSiy fiber defects. Since the electrical defect monitoring method had a similar capture rate for fiber defects as the standard E-beam method, also without nuisance defects, split lots were run using µLoop inspections to identify and resolve the root cause of the killer defect.

Figure 5: Defect inspection results from (a) standard E-beam inspection and (b) the µLoop method.

Root-Cause Identification and Implementation of Process Change

Employing the defect monitoring method on multiple process split lots, the team conducted several short learning cycles and quickly identified the root causes of the fiber defects. They determined that the interaction of three different process modules was responsible for the defects: shallow trench isolation, stacked gate mask, and poly 2 etch. The most manufacturable solution to the problem was to introduce a new middle-of-the-line (MOL) photoresist/masking process.

Once again, E-beam inspection and the defect monitoring method were employed to collect in-line defect data from the CoxSiy layer, with the goal of identifying the specific photoresist process change that eliminated the CoxSiy fiber defects. Figure 6 compares an overlay wafer map from the original process with a map from the process with the new MOL photoresist/masking step. The fiber defects from the original process are located in the vertical clustered streak on the lower left side of the map in Figure 6a. In contrast, the map from the wafers processed using the new MOL photoresist process (Figure 6b) is free of the streak, indicating that fiber defects are not present.

Figure 6: Overlay wafer maps of E-beam scans from the CoxSiy layer from wafers processed using (a) the standard photoresist process and (b) the new photoresist process.

Further evidence that the new photoresist/masking process generates fewer defects than the standard process is presented in Figure 7. Figure 7a compares the total number of defective die resulting from defects on the CoxSiy layer for the standard versus the new process, while Figure 7b compares the end-of-line sort 0 yield bin correlated to the CoxSiy defects for the old versus the new process. Both the defectivity data and the sort 0 yield loss data demonstrate that the new MOL photo-resist/masking process eliminates the CoxSiy fiber defects.

Figure 7: Correlation of E-beam in-line defect scans to end-of-line sort yield losses: (a) shows in-line defectivity resulting from the standard versus the new photoresist process, while (b) shows sort 0 yield bin data for the standard versus the new photoresist process.


Floating gate word line structures on flash memory products have layouts that are uniquely suited to being tested using µLoop technology and E-beam inspection. Spansion’s Fab 25 used this approach to detect small physical defects that were causing a yield excursion in the cobalt silicide layer.

In addition to detecting the CoxSiy fiber defects, the electrical defect monitoring method was used to conduct short-loop experiments to determine the root causes of the defect and to qualify a new MOL photoresist/masking process to correct the problem. The µLoop method was shown to eliminate artifacts, improving inspection times by more than 50% and throughput by more than 70%. Since this work was completed, the method has been employed in the fabrication of Spansion’s 90-nm MirrorBit flash products.


This article is based in part on a paper that was presented at the Eighth Technical and Scientific Meeting of the Centre Régional d’Etudes en Microélectronique Silicium (CREMSI), held October 20–21, 2005, in Fuveau, France. The authors would like to thank several people for their contributions to this article, including Chris Foster, Dan Sutton, Mike Covert, Becky Pinto, and the Fab 25 contamination-free manufacturing (CFM) group, which helped define the yield enhancement experiments and collect the data.

David M. Price is a staff applications engineer in the E-beam inspection division of KLA-Tencor (San Jose). Active in the semiconductor industry for 10 years, he previously worked at Applied Materials. He received a BS in mechanical engineering from Texas Tech University in Lubbock and an MBA from St. Edwards University in Austin, TX. (Price can be reached at 512/462-6225 or

Garrett Long is senior product marketing manager in KLA-Tencor’s reticle and photomask inspection division. With 10 years of experience in the semiconductor industry, he worked at PDF Solutions before joining KLA-Tencor. He began his
career in the area of transistor design and later worked in fab yield ramping. He received a BS in electrical engineering from Carnegie Mellon University in Pittsburgh. (Long can be reached at 408/875-9723 or

Doron Gal, PhD, is a senior product marketing manager in KLA-Tencor’s E-beam inspection division. He received a PhD in physical chemistry from the Weizmann Institute of Science in Israel and then performed postdoctoral research at
the University of Texas in Austin. (Gal can be reached at 408/
875-8706 or

Laura Pressley, PhD, is a senior member of the technical staff in the area of yield management engineering at Spansion’s Fab 25 flash memory manufacturing facility in Austin, TX. Active in the semiconductor industry for 12 years, she previously worked at Motorola and gained project management and process engineering expertise in the areas of etch and yield enhancement. She received a PhD in physical chemistry from the University of Texas in Austin. (Pressley can be reached at 512/602-0196 or

Mike Meyer is the eS31 tool owner in the CFM module at Spansion’s Fab 25 flash memory manufacturing facility in Austin, TX. He has worked in the semiconductor industry for 15 years, including at KLA-Tencor. He has experience in the areas of defect inspection, inspection applications, and yield. He received an AS degree in electronics from DeVry University in Kansas City, KS. (Meyer can be reached at 512/602-8924 or

MicroHome | Search | Current Issue | MicroArchives
Buyers Guide | Media Kit

Questions/comments about MICRO Magazine? E-mail us at

© 2007 Tom Cheyney
All rights reserved.