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Defect/Yield Analysis and Metrology

Performing automated process inspection of C2-open defects using review SEM

Xianghui Xu, Hunglin Chen, and YiLin Sun, Semiconductor Manufacturing International Corp. (SMIC); and Hongbo Jiang, Nurit Raccah, Mike Chang, and Siqun Xiao, Applied Materials

Traditionally, E-beam inspection has complemented bright-field and dark-field optical inspection methods to detect subsurface defects such as open or partially open contacts, vias, and capacitors, which cannot be detected using traditional lamp-based optical inspection tools. E-beam inspection uses voltage contrast to detect defects that exhibit abnormal electrical behavior and are therefore called electrical defects. While its high resolution and large focal depth make E-beam inspection sensitive to defects at the bottoms of high-aspect-ratio structures and the method is becoming more prevalent in the engineering and R&D areas, its wide adoption in production is limited by its low throughput.

Automated scanning electron microscopy (SEM) can detect high-aspect-ratio and voltage-contrast defects at a much lower cost of ownership than E-beam inspection. The difference between SEM and E-beam inspection is that the former captures images at discrete, prespecified locations without having to scan the entire wafer to find random defects.

Automated process inspection (API) using SEM is well suited for detecting systematic defects that appear at known locations. Like traditional wafer inspection systems, SEM/API can monitor excursions by generating defect result files that contain defect counts and locations.

This article presents a case study that was conducted at SMIC’s Fab 2 (Shanghai). The study used a SEMVision G2 focused ion beam (FIB) defect analysis tool from Applied Materials (Santa Clara, CA) to monitor a yield-limiting defect that was undetectable using a traditional lamp-based optical inspection system.

Determining the Source of the Yield Loss

The study commenced when it was discovered that memory devices were suffering from serious yield loss. As illustrated in the wafer-yield bin maps of good versus low-yield wafers in Figure 1, the devices at the wafer edge were primarily responsible for the yield loss. Further investigation found that the problem was caused by capacitor 2 (C2) opens resulting from an incomplete etch step. The top-down SEM images shown in Figure 2 and the FIB cross section shown in Figure 3 indicated that the defect was located at the bottom of a high-aspect-ratio C2 structure, preventing it from being detected using traditional bright-field/dark-field inspectors.

Figure 1: Wafer-yield bin maps of (a) a good wafer and (b) a low-yield wafer. The red areas indicate yield losses caused by C2-open defects.
Figure 2: Top-view SEM images of a C2-open defect.
Figure 3: FIB cross-section image reveals C2-open defect at the bottom of a capacitor (circled feature).

Lacking an E-beam inspection tool, the fab could not pinpoint the problem until an electrical test was performed several weeks later. Defect excursions of this type caused a loss in chip probing (CP) yield of ~40%, and the delay in detecting the excursion affected many work-in-progress wafers. Consequently, it was necessary to discover the root cause of the problem, fix it, and develop an in-line process control monitor to prevent such excursions in the future.

Using SEM/API to Monitor the C2-Open Defect

Since the defects were not random—that is, they could be found in specific regions of the die and wafer—SEM/API was selected to detect and analyze them. Figure 4 presents a schematic diagram of the API flow, which includes four steps:

Figure 4: API process flow includes inspection-site definition, automatic image capture, and defect reporting.

• Step 1: The user defines the die and wafer locations to be inspected (area per site, number of sites per die, and number of die per wafer).

• Step 2: The SEM imaging conditions are defined (accelerating voltage, beam current, scan speed, etc.).

• Step 3: SEM/API is initiated (the SEM automatically scans the designated
locations, collects images, and performs image processing to find the defects).

• Step 4: A defect result file is generated, showing the number of defective sites.

A key issue in SEM/API or E-beam inspection is to control surface charge. For conductive layers, a positive or negative excessive charge can be conducted away without a problem. However, excessive charges on dielectric layers accumulate, causing image distortion and defect detection failures. Several means exist to influence and control the charge balance on the wafer surface, such as accelerating voltage or landing energy, field-of-view size, beam current, scan rate, and a special anti-charging mechanism. An important feature of SEM/API is its ability to minimize image distortion by exercising appropriate charge control.

Because the C2-open problem was more serious and systematic in the dummy area than in the real cell area, inspection sites in both areas were selected. In addition, since the defect issue was more severe at the wafer edge than at the wafer center, more inspection sites were selected at the wafer edge, while the wafer center was inspected for reference purposes. Figure 5 shows the wafer-level sampling plan. Selected for inspection were 19 die per wafer and four sites per die (three in the dummy area and one in the cell area). With a total of 76 sites per wafer, the inspection throughput was four wafers per hour.

Figure 5: API sampling plan showing a wafer map, a die map, and discrete locations within a die for API inspection.

SEM/API combines inspection and defect image grabbing in one step; as it inspects sites, it automatically saves images of defects and their corresponding references. Thus, there is no need to perform defect
review after inspection. In contrast, E-beam inspection requires SEM review after inspection, adding additional time that is normally not considered in the throughput calculation.

Study Results

SEM/API was used to identify the root cause of the incomplete etch problem and set up a proper preventive maintenance (PM) procedure to prevent its recurrence. In addition, SEM/API helped optimize the photo/etch process to improve baseline CP yield and was used to perform in-line inspection for that process step.

Troubleshooting the Chamber Self-Cleaning Step. The first problem detected by SEM/API was a chamber issue. SEM/API results showed that one of the four chambers of an etcher (chamber D) produced a significantly higher percentage of C2-open defects than the other three chambers. A higher percentage of C2-open defects correlated with increased yield loss. This finding pointed to the need to investigate chamber D further. Weeklong monitoring of the chamber, the results of which are presented in Figure 6, revealed that the percentage of C2-open defects dropped dramatically after the chamber underwent PM. However, that percentage rose again after the chamber had been in service for several days. Omitting the chamber self-cleaning step was identified as the root cause of the C2-open defects. Thereafter, a proper chamber self-cleaning step was implemented as part of the PM procedure to prevent further defect excursions.

Figure 6: C2-open monitoring trend chart shows decrease in C2-open defects after PM. The PM was performed toward the end of the wafer run, after which defect counts decreased noticeably.

Process Optimization and Yield Prediction. Figure 7 plots whole-wafer CP yield and wafer-edge CP yield against reported C2-open defect counts. The graph shows that CP yield was inversely proportional to detected C2-open defects. For every 10% increase in detected C2-open defects, wafer-edge CP yield fell by approximately 5% and whole-wafer CP yield fell by 1.2%. To improve yields, feedback from SEM/API was used to optimize the etch/photo process recipes. For example, as shown in Figure 8, the percentage of C2-open defects was found to correlate with radio-frequency (RF) time, with lower RF time resulting in a lower percentage of defects. The optimized photo/etch process recipes reduced the average C2-open defect counts from 22% to 2%, as illustrated in Figure 9. That reduction improved whole-wafer CP baseline yields by 2–3%.

Figure 7: Correlation between full-wafer yield and C2-open defects and between wafer-edge yield and C2-open defects.
Figure 8: Percentage of C2-open defects versus chamber RF time shows a good correlation. Higher chamber RF time corresponds to a greater percentage of C2-open defects.
Figure 9: C2-open defect trend before and after process recipe optimization (dashed line). Average defect counts before and after the optimization was carried out were 16.5 and 1.5, respectively.

In-Line Inspection Using SEM/API. SEM/API is an effective in-line monitoring tool for detecting excursions and providing an early warning that corrective action is required. Hence, SEM/API has been implemented as an in-line inspection step to monitor the etch process. Based on the sampling plan shown in Figure 5, SEM/API is running at a throughput of four wafers per hour. Since its implementation, several C2-open defect excursions have been detected, leading to immediate corrective action. Without SEM/API, C2-open issues would be noticed only after electrical testing several weeks after processing, and many in-progress lots would be processed in defective chambers.


This article describes how API was used successfully to find the root cause of an etch problem, helping to optimize etch/photo process recipes, increase baseline yields, and improve routine in-line monitoring of the etch process to detect excursions early. The study has highlighted some of the advantages of SEM/API. Since it finds abnormal sites based on SEM images, it has higher resolution than traditional bright-field/dark-field or E-beam inspection systems. With greater focal depth and specially designed inner and outer detectors, SEM/API can detect defects located at the bottoms of high-aspect-ratio structures. Moreover, with proper charge control, it can detect subsurface defects using voltage contrast.

Nevertheless, SEM/API also has limitations. For example, because the method requires that inspection locations be preselected, it can be used to monitor systematic defects but is less well suited for monitoring random defects. Thus, SEM/API cannot replace conventional wafer inspection tools. Rather, it complements them.

Another limitation of SEM/API is that it does not reveal detailed within-site information. It indicates only whether a site is normal or abnormal by comparing it to a reference image. In that sense, the method is similar to E-beam inspection. A new option on the SEMVision G2 overcomes this limitation. The new application, quantitative process monitoring (QPM), incorporates a specialized image analysis capability into the SEM that performs fully automated and quantitative process monitoring. For example, in the case of contact etch monitoring, the QPM module provides detailed information about the visited array of the contact, such as the number of vias and contacts with defects, the average size of vias and contacts, and the degree to which a via and contact deviate from the nominal size.


The authors would like to acknowledge the contributions of other members of the SMIC Fab 2 yield enhancement group for their help in collecting the data presented in this article. In addition, the authors would like to thank the applications group of Applied Materials’ PDC Asia Business Management for introducing API and for its continuous support during the course of this work.

Xianghui Xu is an engineer in the yield engineering department of SMIC’s Fab 2 in Shanghai. He received a BS in materials science and engineering from Wuhan University of Science and Technology in China. (Xu can be reached at +86 5080 2000 or

Hunglin Chen is a section manager in the yield engineering department of SMIC. He received a BS in mechanical engineering from National Taipei University of Technology in Taiwan and an MS in applied mechanics from National Taiwan University. (Chen can be reached at +86 5080 200019027 or

YiLin Sun is the department manager of the yield engineering department at SMIC in Shanghai. Before joining SMIC in 2001, he worked at TSMC for nine years in the fields of defect reduction, process integration, yield enhancement, and technology transfer. He received a BS in physics from the National Tsing-Hua University in Hsinchu, Taiwan, in 1988. (Sun can be reached at

Hongbo Jiang is a semiconductor applications engineer who works on SEMVision API applications and in-line FIB technology at Applied Materials in China. He received an MS in materials science and engineering from the Shanghai Institute of Ceramics, Chinese Academy of Sciences. (Jiang can be reached at

Nurit Raccah is a product marketing manager in the wafer inspection division of Applied Materials’ Process Diagnostic and Control business group. In the past five years she has served in various positions in the PDC division, including
as a technologist and an application development engineer. Previously, she worked at Intel Electronics, Israel, as an etch process engineer. She received a BS in chemical engineering and an MS in technology management from the Hebrew
University in Jerusalem. (Raccah can be reached at

Mike Chang is a semiconductor equipment service manager at Applied Materials in China. Previously, he was an applications specialist, working on SEMVision automatic defect classification and API applications. He received an MS in applied mechanics from National Taiwan University in Taipei. (Chang can be reached at

Siqun Xiao, PhD, is the SMIC account general manager in Applied Materials’ PDC group. Before joining the company, he was a sales director at Scientech and a product applications specialist, demo manager, and applications manager in the wafer inspection division of KLA-Tencor. Xiao received an MS in metallurgy from the Rheinisch Westfälische Technische Hochschule Aachen and a PhD in physics from Göttingen University, both in Germany. In addition, he was a postdoctoral fellow at the National Center for Electron Microscopy of the Lawrence Berkeley National Laboratory in Berkeley, CA. (Xiao can be reached at

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