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EDITOR'S PAGE

Propellers spinning mightily

Few conferences see as many IC propellerheads in one place at one time as SPIE Microlithography. This year, more than 5000 professionals came from all over the semiconductor map to San Jose for the conference and exposition. As always, the event reconfirmed the role of patterning as the ultimate enabling (or in some cases, disabling) chipmaking-technology process set. Papers and posters covered the usual range of topics, highlighting everything from root-cause research to development-stage efforts to reports of scanners behaving badly in the fab. The truism “no litho, no chips” has rarely been more apt and the laser-source-like intensity of much of the work more keen.

The lion’s share of the discussion revolved around the 45-, 32-, and 22-nm process generations and how to get there. The definition of those generations varied, depending on whether you were speaking to a logic or memory guy: Is it classified by half-pitch or gate length? Concerns about the readiness of immersion and eventually EUV lithography and their respective tool, materials, and component infrastructures were never far from the surface. Nor was the question of how to achieve true design for manufacturability (DFM).

The technique known alternatively as double or dual exposure or patterning emerged as the solution du jour for 45-nm and perhaps 32-nm, although Intel says it’s dry at 45 and TSMC or the flash memory guys might get wet at that point. Defects, especially those specifically caused by immersion processes, remain the key stumbling block for widespread wet-lithography adoption, although many papers showed that the liquid approach almost matches the more conventional technique’s defect density numbers. If anything, the scanner folks have moved pretty far along the defect learning curve, a largely unknown territory for them before immersion surged to the fore.

IML’s possible extendability also got a boost from an IBM/JSR Micro breakthrough on the high-index liquid (HIL) development front. Working at Big Blue’s Almaden Research Center, the collaborators say that they patterned sub-30-nm lines and spaces using an experimental HIL and advanced resists on an interference immersion-litho test tool named NEMO (named after the submarine captain from Jules Verne’s 20,000 Leagues Under the Sea, not the animated talking fish). The researchers achieved refractive indices of around 1.6 for the lens and fluid and 1.7 for the resist, with an eventual goal of 1.9.

An amusing corollary to the underwater-related appellation of IBM’s NEMO tool was Yan Borodovsky’s designation of the supporters of dry, immersion, and EUV lithography. During the Intel senior fellow’s plenary session speech, he called the dry guys “airmen,” the wet crew “submariners,” and the extreme-UV followers “astronauts.” He presented comparative scorecards for the various litho technologies, showing what each needed to achieve to be successful in terms of CD, overlay, defects, costs of ownership, and other operational and process areas. Borodovsky sees the three approaches converging in a competitive triangle in 2011, with the field narrowing to the submariners and astronauts by 2013.

The campaign to implement design for manufacturability, including optical proximity correction (OPC) and other resolution-enhancement technologies, showed significant year-to-year growth and maturity. Recently, a swarm of related research has reported actual results from the manufacturing space, including data from chipmakers, process and metrology OEMs, and DFM providers. A recurring theme is how the various solutions can achieve such metrics as OPC and process window verifications much faster and more accurately than before, thus accelerating the time to moneymaking yields for the chipmakers.

The DFM space has emerged as one of the most intriguing sectors, with a momentous struggle taking place among EDA stalwarts such as Cadence, Mentor Graphics, and Synopsys and upstarts such as Brion, Invarium, Sagantec, and Sigma-C. The big guys tout their ability to handle most or all of the DFM challenges systematically or holistically, while the littler guys plug their agility and superior technology.

The bar is set pretty high for 45 nm, and extremely high for 32 nm. With design and process complexities growing exponentially, there could be a real shakeout of the DFM players once those with the most effective solutions prove their capabilities to enhance the signal and reduce or eliminate the noise.

Tom Cheyney
Editor

tom.cheyney@cancom.com


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