Novel research materials, devices extend CMOS, suggest revolutionary post-CMOS approaches
THOMAS THEIS (director, physical sciences, IBM Research, T. J. Watson Research Center). Will the silicon CMOS field-effect transistor (FET) still be with us in 2025? Yes, of course! But will it be the dominant technology? Devices are still shrinking at historic rates, but increases in clock speed are stalled by economic limits on acceptable power dissipation—particularly static power dissipation—and by the subtle penalties paid for tolerances that have not scaled with device dimensions. Nevertheless, silicon technology will be extended for at least 10 to 15 years. New materials, device structures, and designs will drive further performance increases at the device level, and cooperative developments in architecture and circuit design will boost system performance.
With the introduction of metal gate electrodes and high-dielectric-constant gate insulators, as well as thinner liners and lower-dielectric-constant materials for wiring, the microelectronics industry is seeking to introduce new materials and device structures at an unprecedented rate. New materials are also the key to nonvolatile memory devices, which are under commercial development. Interface science has never been more important to the microelectronics industry.
How far can this trend be carried? Ideas are being explored that circumvent virtually every previously identified limit of the FET. Despite decades of research, there is still not a clear picture of the “ultimate” FET. Current explorations of semiconductor nanowires and carbon nanotubes suggest that it may have a wirelike geometry, may not be based on silicon, and may be integrated in three dimensions. Furthermore, looking toward 2025, we must ask if there is a device beyond the FET. Seeking to stimulate and accelerate research in this direction, a consortium of Semiconductor Industry Association companies has launched the Nanoelectronics Research Initiative (NRI). NRI-funded research will focus on “non-charge-based” devices—switches that represent logical state by spin orientation, molecular configuration, and other variables.
These developments suggest a continuing economic incentive to build ever-smaller devices. But how will we manufacture at the nanoscale? Current manufacturing processes cannot build much structure into an object at a length scale less than the minimum lithographic dimension, but there is no physical reason that we cannot learn to build objects with complex structure defined down to the atomic scale. Obviously, optical lithography won’t get us there, but new lithographic processes, combined with increasingly sophisticated processes of natural pattern formation (templated and directed self-assembly), certainly will.
The goal is to cap the amount of expensive (low-error-rate) lithographic information that is required to build a complex system. The tricks to making this work include judicious choice of building blocks, clever dynamical steering of the self-assembly process, and design of structures that are tolerant of some defects. Success in this endeavor will ensure continued exponential improvements in the price and performance of information technology for decades to come. Although this is a long-term vision, new materials, processes, and exploratory devices already illustrate the principles.
DANIEL HERR (director, nanomanufacturing sciences research, Semiconductor Research Corp.). Many high-level material and patterning research challenges and requirements that would enable the fabrication of ultimate charge-based information processing technologies are derived from the recommendations of CWG2. The unit is one of five consultative working groups that provide annual industry updates to National Nanotechnology Initiative funding agencies on strategic semiconductor industry–related research needs. While these recommendations transcend specific switch requirements, they assume that charge-based switches will continue to drive information processing technologies through the end of the next decade. With a typical new-technology insertion time of approximately 15 years, it may be difficult to identify and integrate a competitive and scalable alternate, non-charge-based switch before 2020. The following paragraphs summarize some of those research challenges and recommendations.
Fabricating Useful Nanostructures. Radical alternatives are needed that enable the affordable design and scaled fabrication of trillions of identically interconnected electronically useful nanostructures at desired locations on a silicon substrate that connect with the real world. Ultimately, this thematic need addresses the challenges of affordable integration and interconnection of assembled nanocomponents to achieve orders-of-magnitude increases in functional density at lower cost. Key research directions include controlled placement, dimension, arbitrary shape, complexity, composition, reproducibility, and integration of nanostructures; new structures that enable ballistic transport; contacts and atomic-level contact engineering; interconnects; and heat removal. For example, what nanostructures can be fabricated that attain heat removal rates exceeding 1000 W/cm2?
Breakthrough Materials and Nanoscale Characterization Method. It is becoming increasingly difficult for conventional electronic materials and components to satisfy projected deep nanoscale performance and variability requirements. Additionally, dominant properties of nanoscale materials and components may differ from those in bulk form. Key knowledge gaps include:
• Smart photoresists and electronically useful imaging materials. Imaging materials issues include the hierarchical control of line-edge roughness.
• Innovative nanoscale material characterization and metrology. The strategic knowledge gap in understanding the extensibility and limits of characterization and metrology approaches includes the impact of uncertainty and transform-limited spectral linewidths on nanoscale measurements and nondestructive nanoscale dimensional, interface, and defect characterization.
• Materials by design. Research is needed in the design of materials and assembly methods that correlate material structure with nanoscopic properties and enable the formation of useful nanoscale structures with desired functionality.
• Materials to achieve atomically smooth interfaces. Discovery research is needed on the design and synthesis of atomically controlled composite materials (self-assembled low-k and high-k structures, diffusion barrier layers, etc.); conductors; and semiconductor materials with desired functional properties.
• Material properties at the nanoscale. As material and component cross sections shrink, surface and boundary effects are expected to dominate over bulk material properties.
Basic Research on Directed Self-Organization. Directed self-assembly represents one class of potential options for enabling affordable fabrication of future information processing technologies. However, little is understood about the language and tools of directed self-assembling systems. What form and content of applied or embedded information are required to direct material assembly into arbitrarily designed useful nanostructures? Does directed self-assembly offer advantages over conventional subtractive approaches for assembling and integrating materials and nanostructures across a variety of dimensional scales? Exploratory research is needed in novel hybrid top-down (lithographic) and bottom-up approaches (self-assembled), as well as biomimetic methods that leverage existing natural processes.
JAMES HUTCHBY and VICTOR ZHIRNOV (Semiconductor Research Corp.); C. MICHAEL GARNER and GEORGE BOURIANOFF (Intel). While the 2005 ITRS Emerging Research Devices chapter reviews a wide range of evolutionary and revolutionary devices, the most intriguing ones are those proposed for alternate-state variable devices for logic. The challenge that these devices have is to provide computing performance superior to CMOS with lower power consumption while operating at room temperature.To exceed the performance of CMOS in information processing, some of the devices may function with different architectures for special applications and should not be viewed as drop-in replacements for CMOS.
Of the revolutionary devices, those closest to CMOS are the 1-D charge-state devices, which may have the potential for ballistic transport. But to grow them with controlled electronic properties in predefined locations and orientations in the billions per square centimeter and to make robust electrical contacts present serious challenges. Molecular-state devices have been studied for years, but the inability to determine whether the switching is a change in molecular state or changes in contact has made improvement challenging. Recent research using scanning tunneling microscopy and atomic force microscopy has demonstrated molecular switching and been able to determine that changes in metal-molecule bonding angles and spacing can have a dramatic impact on transport properties. The most significant challenges are to deposit stable contacts on the molecular device layer, determining the switching mechanisms and whether they are stable and reliable.
Spin-based device concepts are in the embryonic stage and will require innovative materials to create the properties that will enable room-temperature operation, high on/off ratios, and amplification. The two concepts for semiconductor-based spin devices require either spin injection into a semiconductor from a ferromagnetic material with a spin-selective “drain” or a ferromagnetic semiconductor device region where the spin state is changed by interaction with the carriers, so they are switched when the mediating carrier population increases.
Spin devices need room-temperature ferromagnetic semiconductors and device concepts or materials that can enable gain or amplification. Furthermore, since existing spin-based device concepts use a spin-polarized electron current, it is not clear that they would have any lower power consumption than CMOS. Materials that transport spin without motion of electrons may enable new device operation.
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© 2007 Tom Cheyney
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