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Critical Materials

Monitoring oxidation processes in-line using
a novel characterization technique

Yuri Sokolov and Kathy Anderson, Fairchild Semiconductor

The quality of silicon dioxide and the potential for contamination before, after, and during the oxidation process remain big concerns in the microchip fabrication industry. Common in-line monitors of the silicon–silicon dioxide (Si-SiO2) system include capacitance versus voltage (CV) and triangular voltage sweep (TVS) methods, which require that an MOS structure be built, or surface photo voltage methods, which measure the substrate bulk and are thus relatively insensitive to surface-charge dynamics. These techniques irreversibly alter the sample during measurement. The problems and limitations inherent in these techniques are leading chipmakers to search for less-problematic alternatives that measure critical parameters at and near the wafer surface, where devices are built and operate. One such alternative is the corona oxide semiconductor technique, which analyzes sodium contamination qualitatively.1

This article discusses a surface-charge profiler (SCP) tool that measures depletion width (Wd) and minority-carrier recombination lifetime (τ). The tool also estimates dopant concentrations (Nsc) and charges (Qsc) in the silicon space charge region. The article demonstrates that changes in oxide quality alter the relationship between Wd and τ in predictable ways. The impact of iron, nickel, and copper contaminants on these parameters in bare silicon wafers has been reported elsewhere.2 Hence, this article emphasizes the effect of sodium (Na) contamination on the Si-SiO2 system. It shows that the SCP tool can effectively detect oxide imperfections and the presence of metal impurities in silicon dioxide.

Experimental Procedure

The SCP tool from QC Solutions (Billerica, MA) uses a surface photo voltage method to measure the impact of charges in an oxide, at the oxide-silicon interface, and at the resulting space charge region. The measurement is performed by flashing a light onto the wafer at a depth of 0.4 µm and evaluating the real and imaginary components of the returning ac-surface photo voltage signal to derive values for two critical parameters: Wd and τ. The tool uses the resulting Wd measurement to compute a value for the dopant concentration in the substrate beneath the oxide and for charges in the silicon space charge region, which is balanced with the total charge in the oxide. The SCP also produces a wafer map for each of these parameters.

An experiment at Fairchild Semiconductor (West Jordan, UT) tested p-type silicon wafers with a boron concentration from 5 × 1014 to 5 × 1015/cm3. A 100-nm-thick thermal oxide layer was grown. A grown oxide results in the creation of positive charges in the vicinity of the interface. The interface charges invert the lightly doped silicon subsurface, producing a depletion region beneath the oxide. The depth of the silicon space charge region measurement depends on the dopant concentration in the substrate, the amount of charge at the interface, and any charges in the oxide. Another parameter affected by the charges in the Si-SiO2 system is τ. As the number of charges at the Si-SiO2 system increases, the extra charges result in the redistribution and creation of extra recombination centers, which affect the value of τ.

Wd and τ values were measured in the substrate before and after thermal oxidation. Before the SCP measurement, each bare wafer tested was subjected to a rapid optical surface treatment (ROST) to remove organics that may have adsorbed onto the wafer surface. The presence of such organics alters the wafer’s surface potential, thereby affecting the resulting Wd value. ROST treatment is not necessary for oxidized wafers because, aside from Nsc, the depletion width for oxidized wafers is primarily driven by Si-SiO2 interface charges and charges in the oxide.

For perfectly grown and externally uncontaminated oxide layers, the t value was 25 to 40 microseconds, and the Wd value was 0.8 ± 0.1 µm for an Nsc of about 1 × 1015/cm–3. Any deviations from these parameters were considered evidence of oxide imperfection or a contamination occurrence. Hence, the combination of τ and the percentage change of Wd after thermal oxidation served as critical parameters for oxide qualification.

In addition to monitoring the oxidation quality of production test wafers, the investigators measured test wafers that were intentionally contaminated with sodium, which was implanted to a depth of about 100 nm from the bare silicon surface. For other wafers with a pregrown oxide layer of either 40 or 100 nm, sodium ions were implanted to a depth of 10 nm. The doses used were from 1 × 1010 to 1 × 1012/cm2.

The SCP technique was applied for the first time not just to detect postprocess metal contaminants in the furnace and the silicon–silicon dioxide, as described in the literature.2 It was also used to measure process improvement. A furnace that had been contaminated with sodium was subjected to a high-temperature clean process, including a chlorine source. An uncontaminated bare silicon wafer was scanned using SCP and then placed in a 700°C furnace for 30 seconds. Only nitrogen flowed into the furnace. After being removed from the furnace, the wafer was cooled and retested. The results indicated that sodium was still present in the furnace.

The high-temperature clean process was modified by reducing the annealing temperature below 1200°C, and the test was repeated. Results from the second test indicated that sodium was no longer present at a level detectable using this testing procedure.

Some oxidized wafers were illuminated with ultraviolet (UV) light (the dominant line λ = 254 nm) to distinguish sodium contamination from other types of metal contamination. (UV illumination is one of the SCP tool’s functions.) The wafers were tested for Wd and τ before and after UV treatment.

Results and Discussion

Figure 1 shows how postoxidation Wd varied versus the dopant concentration in the substrate. Each data point represents a mean of the measurements from 10 to 20 test wafers with “ideal”-quality oxide. Subsequent TVS plotting proved the absence of mobile ions in these wafers. The calibration curve in Figure 1 enabled the investigators to create a model that predicted the expected postoxidation depletion width (Wd-post) versus initial Nsc with 10% confidence. Initial Nsc, in turn, was derived from the preoxidation depletion width (Wd-pre).

Figure 1: Postoxidation depletion width versus silicon doping concentration. The data were derived from uncontaminated wafers. (Wd average = 0.2188048 + 5.9676 × 1014 recip[Nsc average].)

Contaminants introduced during oxidation contribute to the interface charge state and/or produce an image charge to the substrate, thereby changing Wd. Monitoring the percent change of the depletion width, ΔWd/Wd-pre, enabled the investigators to exclude variation in the initial dopant
concentration as a component of the total variation in the monitor. Wafer-to-wafer variation in ΔWd/Wd-pre was attributed solely to variation in the interface and/or oxide charges. Another benefit of monitoring the percent change in depletion width as opposed to postoxidation Wd alone is that this metric is conveniently insensitive to the within-wafer nonuniformity of Wd that is common in oxidized test wafers.

Wafers with a preprocess dopant concentration equal to 1 × 1015/cm–3 or less, as measured by the SCP, have been found to be most appropriate for oxide characterization. A more heavily doped substrate causes Wd to be too shallow and the derived Qsc values to become questionable.

Minority-carrier recombination lifetime is another critical parameter that significantly affects the presence of a contaminant. An abnormally low τ indicates the presence of extra recombination centers in the vicinity of the interface. Lifetime degradation, coupled with reduced Wd in comparison with preoxidation performance, is considered a signature of charged contaminants.

The space charge is a convenient qualification parameter because it represents the total oxide charge. Qsc = qNscWd and is linearly proportional to Wd for Nsc = constant. It should be noted that while the depletion width measurement is a direct measurement, the tool’s derivations of Nsc and Qsc are not. A boundary condition requires that the depletion width be at its maximum. The relationship between Wd and Nsc follows a known model:

However, Nsc varies from wafer to wafer. Because Wd is observed to be inversely proportional to the square root of Nsc, it follows that for variable wafer-to-wafer Nsc, Wd is inversely proportional to Qsc.

Fingerprint Test

A concern in wafer fabrication is that sodium can be introduced onto the wafer during handling. To test the SCP tool’s sensitivity to this problem, a bare wafer with a native oxide was intentionally imprinted by (A) two bare fingers; (B) two gloved, saliva-covered fingers; and (C) two gloved fingers that had been used for head scratching. Before and after imprinting, the SCP tool was used to scan the wafer, measuring and mapping Wd and τ. The resulting Wd measurements after imprinting are presented in Figures 2a and 2b.

Figure 2: Wd and lifetime data from a fingerprinted wafer: (a) contour plot of Wd, and (b) Wd versus lifetime by area. A = fingerprints caused by bare fingers, B = gloved, saliva-covered fingers, C = gloved fingers after head scratching, and D = undisturbed bare silicon area.

All of the fingerprints were distinctly identified in lifetime and depletion width maps, the latter of which is shown in Figure 2a. The imprinted areas in the map correspond to the lifetime decrease and Wd increase presented in the graph in Figure 2b. Each data point in Figure 2b corresponds to a particular point on the wafer map. The bare fingers had the most severe impact on the wafer, while the gloved fingers used for head scratching had the least severe impact. Despite the pronounced visual effect seen in Figure 2a, the critical parameters for Wd and τ in the imprinted areas were still within the control limits.

This test revealed that bare fingers introduce sodium or other possible species onto the silicon surface. Foreign ions are added to the network of the natural positive charges already occupying the p-type silicon surface, affecting Wd and the surface recombination lifetime.

When the experiment was repeated using previously oxidized wafers with an oxide thickness of 60 nm, the impact of finger contact with the wafer surface on Wd and τ was barely recognizable. When the oxide thickness was 100 nm, no effect whatsoever was detected. Hence, the density of foreign charges delivered via fingerprints seems to be too small to be detected over the charges’ interaction with the interface and existing oxide charges.

To probe for mobile ions, an MOS structure was formed on the imprinted wafers, and TVS measurements were performed on the localized contaminated regions. The estimated level of electrically active sodium turned out to be an insignificant ~5 × 109/cm–2.

Wafers Implanted with Sodium

The investigators then studied wafers with similar starting Nsc levels into which sodium was intentionally implanted into the oxide at concentrations equal to or more than 1 × 1015/cm–3. Figures 3a and 3b show the τ and Qsc before and after implantation for two wafers with different oxide thickness (96 and 40 nm). While the scattering of Wd and τ values across the oxidized wafers differed depending on the oxide thickness, as shown in the maps in Figures 3a and 3b, τ decreased dramatically and Qsc increased in the substrate after sodium implant.

Figure 3: Lifetime versus Qsc for oxidized wafers before and after Na implantation: (a) oxide thickness = 96 nm, and (b) oxide thickness = 40 nm. The implanted species for both wafers was Na+ at 5 × 1011/cm2.

It is assumed that the extent of lifetime degradation and Wd narrowing should depend not only on the contaminant’s concentration, but also on the location of the ions in the oxide film. If Na+ occupies the oxide surface, as in the implanted case, it changes the capacitance of the oxide and redistributes the interface charges that influence Wd and τ in one way. In production, however, it is more common for sodium ions to be introduced into the oxide so that they mostly occupy the interface, causing Wd and τ to change in another way. Because of the variety of possible contaminant locations and their differing effects on Wd and τ, final Wd and τ values are not used to quantitatively deduce a value for contaminant concentration. However, they can be used to monitor process conditions and detect relative abnormalities.

Monitoring in the Production Line

Previous research has concentrated on the use of bare silicon test wafers to study in-line SCP monitoring of metal contaminants in oxidation/ diffusion furnaces.3 This article, in contrast, focuses on the use of oxidized silicon test wafers. More than 500 wafer runs were tested in multiple furnaces. All wafers were processed using the same oxidation recipe.

Examples of τ and Wd control charts are shown in Figures 4a and 4b. All data with t < 25 microseconds and shallow Wd-post values (that is, DWd/Wd-pre < 0) were considered out of control and suspected of contamination. Because the particular target was Na+ contamination, all wafers with abnormal results were subsequently measured using the routine CV/TVS procedure to identify sodium in the oxide. The TVS results confirmed that less than 10% of the abnormal wafers were contaminated with sodium.

Figure 4: In-line monitor control charts for (a) lifetime, and (b) Wd. Preoxidation Nsc for these wafers ranged from 1 × 1015 to 3 × 1015/cm–3.

The deviation of critical parameters from the baseline is not necessarily related to a particular Na+ contamination event, but rather indicates the presence of accumulated defects such as oxide trap charges, metal impurities, or improper charging of the interface because of insufficient annealing or poor oxidation. Most of the failed wafers shown in Figure 4 were assumed to be slightly contaminated with iron, presumably from the silicon carbide (SiC) cassettes and/or dummy wafers with which the test wafers were processed.

The new characterization technique saves enormous amounts of qualification time. The SCP test itself takes four minutes and provides immediate feedback on the status of a furnace. The turnaround time for SCP testing is 10 times faster than that for CV measurements. While all preparations for SCP testing require about four hours, 10 hours on average are required using the conventional CV technique. The SCP pass rate in the test described here was 90% for non-high-temperature furnaces using quartz tubes and cassettes, as opposed to 45% for high-temperature furnaces with SiC tubes and cassettes.

Therefore, the SCP monitor has obvious benefits: It does not require MOS preparation; it offers short turnaround times for gathering information about the condition of the device area of the substrate on either bare or oxidized silicon; it provides greater Nsc/Qsc measurement accuracy than the CV approach; it can detect ionized metal impurities; and its test results can be used to improve processes that are sensitive to the properties of the Si-SiO2 interface.

The SCP tool was used to measure process improvements. Evidence of this is illustrated in Figure 5, which compares the lifetime results of a test wafer that was run before process modification and a wafer that was run after the modification. First, an oxidation furnace was contaminated with sodium and then used to perform a high-temperature clean process, including a chlorine specie to remove or getter any mobile sodium in the system. A bare test wafer with ideal Wd and lifetime values was then exposed to the furnace and measured.

Figure 5: Point-to-point lifetime values (microseconds) of two test wafers that were measured before and after process improvement in a high-temperature furnace.

Because the lifetime values were abnormally low (as shown by the red plots in Figure 5), the effectiveness of the high-temperature clean process was thought to be inadequate. Therefore, the recipe was modified by reducing the annealing temperature below 1200°C, and another bare test wafer with ideal Wd and lifetime values was run in the still-contaminated furnace. A significant process improvement was achieved, as demonstrated by the green plots in Figure 5.

This improvement action was explained by the inability of chlorine to getter sodium appropriately at elevated temperatures. Above 1150°C in an inert-gas ambient, the chlorine complex can break down, causing it to diffuse out of the oxide. In contrast, annealing temperatures below 1150°C result in a diminished gettering effect. This effect can be explained by the failure to form a chemical complex that getters (provided the chlorine concentration is enough to ensure gettering). For atmospheric oxidation, there is a specific temperature range within which chlorine getters sodium contamination appropriately.

UV Treatment and Sodium Identification

To qualitatively identify sodium using the SCP tool, elaborate and time-consuming time-relaxation experiments are required.2 That type of testing, although reliable, cannot feasibly be implemented in a production environment. A potentially workable alternative is UV treatment, which the SCP tool can perform.

It has been theorized that sodium ions in an MOS structure can be passivated using UV illumination.3 Within a period of 100 hours after UV treatment even at 200°C, most neutralized sodium atoms do not release electrons and become positive ions again. Such a remarkably stable effect cannot be explained merely by a decrease in carrier trap density that originates from organic and inorganic contaminants commonly existing on the wafer surface or at the Si-SiO2 interface. In such cases, the lifetime rapidly decreases within minutes after UV irradiation.4

These preliminary test results indicate that the lifetime of oxidized wafers suspected of being contaminated with sodium improves significantly after the wafers undergo UV treatment. The restored lifetime was maintained for more than 48 hours, supporting published findings.3 Therefore, in-line SCP monitoring of oxidized wafers using interim UV illumination should help to distinguish between different types of contaminants (sodium is present in wafers in which a low recombination lifetime value increases significantly after UV treatment). Otherwise, the presence of other contaminants, most commonly iron, should cause lifetime degradation that is not reversed after UV illumination.

Because adding an MOS structure to the wafer before UV treatment would destroy the samples and render post-UV SCP measurements meaningless, CV or TVS should not be used before UV treatment to confirm that sodium causes lower lifetime results. Nor can they be used after UV treatment because of the treatment’s stable passivating effect. The addition of a UV treatment step to the SCP testing sequence has the potential for distinguishing sodium from other contaminants at a rate fast enough and with a method simple enough to be implemented as part of a standard production process qualification procedure. Further testing is required to establish monitor feasibility, reliability, and limitations.


The surface-charge profiler can be used to monitor the impact of oxidation processes, equipment conditions, and handling on the Si-SiO2 system. Because varying Nsc values affect the measured depletion width, users should select DWd/Wd-pre as the parameter to monitor changes in charge before and after oxidation. Since it is possible that a particular contaminant may introduce a significant number of recombination centers yet have an insignificant effect on DWd/Wd-pre, it is recommended that users monitor the recombination lifetime as well.

Currently, there is no convenient production-worthy in-line monitor to determine whether the low lifetime and Wd values of a wafer are caused by sodium or some other contaminant. However, further research in the area of UV treatment can potentially lead to the development of such a monitor.


1. J Bickley, “Quantox Non-Contact Oxide Monitoring System,” Keithley Technology Paper (Cleveland: Keithly, 1995).

2. Y Sokolov, “Metal Contaminant Monitoring in a Silicon Wafer’s Space Charge Region,” Semiconductor International [online] August 2005 [cited 18 January 2006]; available from Internet:

3. I Manabu et al., “Passivation of Sodium Ions in MOS by Annealing with UV Light,” Journal of the Electrochemical Society 143, no. 10 (1996): 3359–3365.

4. K Katayama et al., “Effect of UV Irradiation on Noncontact Laser Microwave Lifetime Measurement,” Japanese Journal of Applied Physics 30, no. 11B (1991): L1907–L1910.

Yuri Sokolov, PhD, is a staff process engineer in the diffusion, thin-film, and epi areas at Fairchild Semiconductor in West Jordan, UT. He received a PhD in solid-state physics from the Kharkov Polytechnic University in Ukraine. (Sokolov can be reached at 801/562-7158 or

Kathy Anderson was a gate oxidation and diffusion process engineer at Fairchild Semiconductor. She received a BS in chemical engineering from Brigham Young University in Provo, UT. (Anderson can be reached at

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