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Meeting the future challenges of high-k
gate dielectrics and metal gates

Koen Snoeckx, Wim Deweerd, Annelies Delabie,
Sven Van Elshocht, and Stefan De Gendt, IMEC

At the 45-nm node and beyond, silicon oxynitride (SiON) will have reached its limits in the manufacture
of low-standby-power (LSTP) devices. High-k dielectrics are being prepared to take over. The correct choice of gate-electrode material, in particular metal gates, will have a great influence on future technology developments. Performance, threshold voltage, and gate leakage will be the most important concerns affecting the implementation of these new materials. In addition, scalability and manufacturability will be key factors in deciding which materials to use. As time progresses, more and more solutions are being discovered, heralding the introduction of high-k materials into production.

With the need for thinner gate stacks and ever-higher device performance, gate leakage issues arise. Both 90- and 65-nm devices suffer from gate leakage because of critical heat generation and power consumption problems. Especially for LSTP applications, lowering gate leakage—and, therefore, power consumption—is crucial. Neither SiON nor SiO2 can achieve the requirements set forth in the International Technology Roadmap for Semiconductors. The most promising candidates to replace SiON (and SiO2) are hafnium (Hf)-based high-k dielectrics.1 Materials with a high dielectric constant (k-value) enable manufacturers to deposit physically thicker layers to achieve the same electrical performance as can be achieved using a thin SiO2 layer. That relationship is expressed as equivalent oxide thickness (EOT) or capacitance equivalent thickness (CET). High-k materials offer better downscaling potential than SiON.

With the introduction of novel high-k materials to achieve lower leakage and optimal performance, novel problems emerge, including decreased charge mobility, lower thermal stability, and difficult-to-control threshold voltages. However, extensive studies on high-k materials in the past few years have resulted in important improvements. Test results indicate that short-term 45-nm LSTP specifications can be reached using hafnium-based gate stacks. Moreover, when combined with metal gates—instead of standard polysilicon—hafnium-based solutions might be valid for even further scaling. A key challenge for the future of metal gates will be to find and integrate a combination of metals with the correct work function.

Primarily because of their electrical characteristics, the most promising high-k materials for replacing SiON in the near future are hafnium silicates (HfSiOx). HfSiOx layers, in direct contact with silicon, have high k-values, thermodynamic stability, and a low leakage current. Using standard chemical-vapor deposition techniques, IMEC (Leuven, Belgium) has been able to deposit a wide range of HfSiOx layers. For gate electrodes, several options were investigated, including traditional polysilicon, fully silicided (FUSI) gates, and inserted metal gates. Researchers investigated several parameters: the materials’ thermal stability, performance (as a function of charge mobility), power consumption (determined by gate leakage), and the influence of nitridation on these parameters. They have concluded that higher hafnium content enables EOT scaling and leakage-current improvements as long as the selected electrode material can tolerate greater hafnium levels.

Ensuring Stability Using Nitrogen

Postdeposition thermal stability is an important requirement for high-k materials. But as hafnium content increases, high-k films become susceptible to lower crystallization onset temperatures, which create unwanted phase segregation. As shown in Figure 1, this effect can be countered by the implantation of nitrogen before source/drain activation, which is known to prevent boron from penetrating from the polysilicon gate into the gate dielectric of PMOS transistors. Generally, postdeposition annealing is used to implant nitrogen. The anneal is performed either in NH3 or through decoupled plasma nitridation (DPN) in an N2 atmosphere followed by a postnitridation anneal (PNA).

Figure 1: X-ray diffraction measurements of crystallization onset temperature versus hafnium content for atomic-layer-deposited HfSiOx layers. For a given hafnium content, nitridation clearly increases the crystallization onset temperature and thus the thermal stability of high-k layers.

Extensive testing was performed at IMEC to determine the effect of nitridation on hafnium-based films. Results were obtained through Fourier-transform infrared spectroscopy and x-ray diffraction measurements on hafnium-based films deposited using atomic-layer chemical-vapor deposition. When nitridation was not performed, clear phase segregation was visible after source/drain activation. However, when nitridation was performed, the spectra of the high-k films were identical before and after the temperature step. It was therefore concluded that nitridation improves the thermal stability of hafnium-based high-k layers.2

Limitations of Using Polysilicon

Polysilicon is one of several gate-electrode materials that can be used on top of the high-k dielectric film. However, while the EOT target can be relatively easily reached by increasing the hafnium concentration in conjunction with polysilicon, increased hafnium concentrations lower yields and cause leakage (although not as seriously as with SiON). Consequently, combining a high-k dielectric with traditional polysilicon gate electrodes is problematic. Furthermore, higher hafnium concentrations have a negative effect on threshold voltage (Vt) control, especially in PFETs. Finally, increased hafnium concentrations cause charge mobility (and thus performance) to stay relatively far from theoretical values and below the charge mobility of SiON-based gate stacks.3

Several techniques are available to resolve these problems. For example, nitridation, which is mandatory when using polysilicon, has a positive influence on gate leakage, but only at the expense of decreased performance. To influence Vt, the use of epitaxial silicon-germanium channels is a popular approach, including at IMEC. Boron counterdoping and aluminum oxide caps on top of HfSiOx are other techniques. The big question, however, is whether the combination of interventions has an overall beneficial effect on the final specifications. In addition, all of these techniques require reengineering of the channel, which involves process control, implantation, and other issues. Although experimental results indicate that the huge effort invested in testing these methods will likely pay off in achieving the short-term specifications, improvements are relatively marginal and not scalable for future technology nodes.

In short, while EOT scaling specifications are relatively easy to reach for high-k/polysilicon stacks, Vt control and gate leakage are critical. Although channel engineering might temporarily resolve this issue, polysilicon’s depletion effect will always prevent further scaling. Thus, high-k/polysilicon gate stacks can meet 45-nm specifications, but for LSTP applications, they will remain a one-generation solution if higher leakage is tolerated. It may therefore be more rewarding to develop metal gates or FUSI gates.

To overcome the poly-depletion effect, polysilicon can be completely converted to silicide to form a FUSI gate. The FUSI approach is an in-between solution because it appears to have some of the advantages of metal gates while also displaying some of the limitations of polysilicon. For example, while a polydepletion layer is absent in FUSI gates, enabling CET scaling without compromising on mobility and performance, gate leakage may remain a difficulty because of the limited amount of hafnium that can be incorporated in the FUSI structure.

In terms of process complexity, FUSI gates can be considered a viable extension of polysilicon gate technology. Promising results with symmetrical Vt for PMOS and NMOS transistors have been achieved at IMEC, pointing the way toward a manufacturable process. FUSI is therefore a good candidate to replace SiON in the manufacture of gate stacks. Nevertheless, the process is complex; the narrow process window of the silicidation step can be a critical stumbling block in the way of the technology’s industrial implementation.4,5

Developing Metal-Gate Electrodes

A more radical transformation of gate-stack technology than the FUSI approach is to completely abandon the use of polysilicon and switch to metal-gate electrodes. The first important advantage of metal-gate electrodes is that metal gates allow higher hafnium content in the high-k layer (up to 100% in HfO2). Gate leakage decreases considerably, and EOT scaling becomes less of an issue thanks to the increase in k-value. In addition, charge mobility with metal gates is 25–30% greater than with polysilicon, enabling better performance. However, important questions remain to be answered.

The first question relates to the necessity of nitridation. Nitridation is performed to suppress boron penetration, but since boron penetration does not occur with metal gates, researchers must determine whether it is still beneficial to perform nitridation. Because nitridation increases the crystallization onset temperature, it reduces the number of leakage paths that originate from phase separation. At the same time, however, it decreases performance (charge mobility) and likely also lowers device re-liability and lifetime. With a higher hafnium content, equivalent oxide thickness (EOT) scalability improves, and improved EOT scalability reduces leakage. Consequently, nitridation is less necessary to control electrical performance.

Since nitridation is not mandatory in the manufacture of metal gates, many engineers would prefer to eliminate it altogether from the process flow. In the meantime, the key is to strike a balance between gate leakage, EOT, and charge mobility. Figure 2 presents the relationship between EOT
and gate leakage.

Figure 2: High-k materials in combination with metal gates offer better scaling capabilities (EOT) and decreased gate leakage (Jg) than polysilicon.

While the transition to metal gates will be far from straightforward, metal-gate research—including efforts to optimize the silicidation process—have already resulted in performance benefits that outstrip those associated with the use of polysilicon. For example, metal-gate-based test structures offer lower leakage or higher performance than polysilicon-based ones. As shown in Figure 3, metal gates achieve an order of magnitude lower leakage for the same target performance, plotted as a function of transconductance (gm). Or, for the same leakage current, metal gates achieve considerably higher performance than polysilicon.

Figure 3: Performance comparison between high-k/polysilicon gate stacks and high-k/metal gate stacks. Polysilicon does not meet the gate-leakage requirement for LSTP applications. The performance of the metal-gate measurements at the bottom left were limited because EOT was too high.

Trend lines indicate that hafnium-based high-k materials, especially ones with a higher hafnium content such as HfO2, have the potential to
satisfy 45-nm specifications.

The operating voltage for LSTP applications is typically 1.1 V. To leave sufficient room for operating voltages (Vg–Vt), threshold voltage must be kept within limits. However, current metal-gate results have been obtained with devices in overdrive (Vt = +0.6 V). That is, research results can be obtained by testing devices at Vt = +0.6 V, while assuming the correct operating voltage. IMEC results have been obtained with metal gates composed of tantalum nitride. Future work will focus on finding a combination of metals with the correct engineered work function to achieve good Vt. In addition, current and future research will concentrate on reliability studies, but preliminary test results are promising.6

Figure 4: Comparison among different technologies for LSTP applications. In future LSTP generations, metal gates together with nonnitrided stacks with high hafnium levels are a promising gate-stack alternative, assuming that metals with the appropriate work function are found.


High-k dielectrics in combination with polysilicon, FUSI, or metal-gate electrodes are definite candidates to replace SiON in LSTP devices. Polysilicon’s scalability, however, is limited because of the poly-depletion effect. Even within scalability margins, recent polysilicon improvements have been limited. FUSI gates, on the other hand, are a valuable alternative to polysilicon, but they have some of the same downsides. Moreover, FUSI process integration issues may be more problematic than they appear at first sight.

In contrast to the other technologies, metal gates have the potential to meet 45-nm specifications and offer room for scalability when used in conjunction with materials with a high hafnium content such as HfO2, as demonstrated in Figure 4. For the near future, the biggest challenge will be to find an appropriate metal with a work function that will make it possible to reach the LSTP Vt target. The discovery of such a metal will largely determine whether high-k materials in combination with metal gates can be used in future CMOS applications.


1. S Van Elshocht et al., “Electrical Characterization of Capacitors with AVD-Deposited Hafnium Silicates as High-k Gate Dielectric,” Journal of the Electrochemical Society 152, no. 11 (2005): F185–F189.

2. A Delabie et al., “ALD HfO2 Surface Preparation Study,” in Proceedings of the MRS 2002 Fall Symposium vol. 745 (Warrendale, PA: Materials Research Society, 2003), 179–184.

3. W Deweerd et al., “Potential Remedies for the Vt/Vfb-Shift Problem of Hf/Polysilicon–Based Gate Stacks: A Solution-Based Survey,” Microelectronics Reliability 45, nos. 5–6 (2005): 786–789.

4. KG Anil et al., “CMP-less Integration of Fully Ni-Silicided Metal Gates in FinFETs by Simultaneous Silicidation of the Source, Drain, and the Gate Using a Novel Dual Hard Mask Approach,” in Symposium on VLSI Technology. Digest of Technical Papers (Piscataway, NJ: IEEE, 2005), 198–199.

5. JA Kittl et al., “Scalability of Ni FUSI Gate Processes: Phase
and Vt Control to 30 nm Gate Lengths,” in Symposium on VLSI Technology. Digest of Technical Papers (Piscataway, NJ: IEEE, 2005), 72–73.

6. S De Gendt et al., “High-k Stack Engineering—Towards Meeting Low Standby Power and High Performance Targets,” in Proceedings of the Electrochemical Society vol. 2005-05 (Pennington, NJ: Electrochemical Society: 2005), 109–117.

Koen Snoeckx is a scientific editor at IMEC, where he is responsible for authoring and editing the organization’s technical documents and publications. He received a master’s degree in biochemistry from the University of Antwerp in Belgium. (Snoeckx can be reached at +32 16 288245 or

Wim Deweerd, PhD, works in the silicon process and device technology division at IMEC (Leuven, Belgium). He began in the division as a process and integration engineer in the 200-mm pilot line and then became a senior scientist in the high-k gate-stack program. Deweerd is active in the field of LSTP and LOP integration using hafnium silicates for the 45-nm node and researches high-k scalability for future CMOS generations. He received MS and PhD degrees in nuclear solid-state physics from the Katholieke Universiteit (KU) Leuven. (Deweerd can be reached at +32 16 288128 or

Annelies Delabie, PhD, is a scientist in the high-k metal-gate program of IMEC’s silicon process and device technology division, where she works on the deposition of thin films using atomic layer deposition. Delabie is the coauthor of 28 publications in international journals. She received an MS in inorganic chemistry and a PhD in quantum chemistry from the University of Leuven. (Delabie can be reached at +32 16 281220 or

Sven Van Elshocht, PhD, is a scientist in the high-k metal-gate program at IMEC, where he works on the characterization of hafnium-based and alternative gate dielectrics. He began at IMEC in the silicon process and device technology division. Van Elshocht is coauthor of 32 papers on nonlinear optics or high-k materials in various international journals. He received MS and PhD degrees in physical chemistry from KU Leuven. (Van Elshocht can be reached at +32 16 288098 or

Stefan De Gendt, PhD, is program manager of IMEC’s high-k and metal-gate program, which involves partnerships with several IC and equipment manufacturers. He joined IMEC as a research scientist in 1996 to research and develop ultraclean processes for silicon cleaning and pretreatment. His main research topics dealt with metallic contamination control and the development of ozonated chemistries. In 1999, De Gendt became involved in research on alternative dielectric (high-k) materials for gate-stack applications. Since 2003, he has been affiliated with the chemistry department at KU Leuven. The author or coauthor of more than 100 publications, he received BS, MS, and PhD degrees in chemistry from the University of Antwerp. (De Gendt can be reached at +32 16 281386 or

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