Infineon uses vertical structure to optimize on-resistance in power MOS devices
Consumer products have become a leading technological and market driver of the semiconductor industry, fostering an ever-increasing demand for power density in devices targeted for that segment. Chipmakers have found that by reducing power losses, they can boost real power without going to larger chips. Their efforts have helped foster a burgeoning market for more-efficient power devices.
In the late 1990s, Infineon (then Siemens) introduced a line of power MOS chips they dubbed CoolMOS, aimed at switch-mode power supplies. The company claimed that the chips had much lower on-state resistance than regular MOSFETs, thus reducing conduction-based power losses and improving switching time. This breakthrough was accomplished in a chip area one-fifth the size of an equivalent surface-doped MOSFET.
The high breakdown voltage required of power NMOSFETs usually mandates a thick, low-doped n-epitaxial drift layer in the device between the source diffusion on the top surface and the drain diffusion on the backside. This kind of device structure essentially dictates that the higher the breakdown voltage (thicker epi), the higher the associated on-resistance—since the current flow moves vertically through the drift layer—and the slower the switching speed.
The CoolMOS structure gets around this problem by increasing the n– epi doping by an order of magnitude and introducing compensating p– columns that keep the integrated charge in the drift layer at the appropriate level for the required breakdown voltage. The basic structure features the p– columns embedded in an n– epitaxial layer on an n+ substrate.
In the “on” state, the current is conducted through the n– epi regions, and in reverse bias, both the columns and the epi deplete completely, giving the breakdown voltage equivalent to the integrated doping of the epi layer. Since the n– epi is more highly doped than a conventional device, the lower resistance allows a smaller chip for the same on-resistance or a higher power for the same size chip. The depth of the epi layer and columns can be adjusted to achieve the required specifications: Infineon has CoolMOS products ranging from 500- to 1000-V tolerance.
This sounds fine in theory, but how does it work in practice?
Chipworks analyzed an Infineon SPP02N80C3 CoolMOS n-channel device, rated at 2 A and 800 V, with an on-state resistance of 2.4 W. The C3 designates the third generation of the technology, and it was manufactured at the Villach fab in Austria.
Figure 1 shows a photo of the 4.3-mm2 die, showing the gate contact on the left and the remains of the aluminum 10-mil source-contact wire on the right. Figure 2 depicts a cross section of the die; the die is 210 µm thick, with the top 60 µm being the n– epi layer. On close examination, one can almost see some structures in the epi layer, which are the p– columns.
Considering the low doping levels in the epi, the scanning capacitance microscope (SCM) is the imaging tool of choice, since it distinguishes n and p doping best in lightly doped samples. Figure 3 is an SCM plot of two p– columns, 42 µm deep, clearly showing the undulating structure that offers clues about how the columns form. The microscope does not distinguish the metal and poly at the sample surface. Secondary ion mass spectroscopy and spreading resistance probe analyses reveal that the substrate was antimony-doped to ~5 × 1017; the epi is phosphorus-doped to ~5 × 1014; and the columns are boron-doped to ~1 × 1015 atoms/cm2.
Given the shape of the columns, it seems clear that they are made by depositing successive epitaxial layers (in this case, seven layers), implanting boron after each epi growth step, and outdiffusing to merge the boron implants. Obviously, the dose and thermal budgets must be carefully tuned to obtain the required doping uniformity.
At the surface, the device looks fairly conventional. The columns extend from the p-wells that underlap the gate electrode and define the channel length. Within the p-well there is a p+ contact region and the n+ source diffusion, as shown in Figure 4. The source metal is 5.5 µm thick and the gate polysilicon is ~0.5 µm thick, with a channel length of ~2 µm and a 90-nm gate oxide. There are about 12,400 cells in this device.
In plan view, one can see that the cells are hexagonally shaped, defined by the gate, in a hexagonal array. Figure 5 shows the polysilicon pattern (left) and the diffusion outlines (right). Figure 6, an SCM image of the array beveled into the p-wells, indicates that they are circular, with the same hexagonal layout. The p+ contact regions can be seen faintly in the center of each well.
The CoolMOS devices offer a good example of the innovative design seen in other chip market segments, yet they do so without employing deep submicron technology. Because of this, Infineon is well placed to take some of the oft-ignored but essential power-chip market that exists in the shadow of the much-hyped processor and memory segments. —Dick James
This report is one of a regular series of device-level process analyses, written exclusively for MICRO by Chipworks’ senior technology adviser, Dick James, a 30-year veteran of the semiconductor industry. Chipworks is an Ottawa, Canada–based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. The technical intelligence customers are usually within manufacturing companies, performing product development, or doing strategic marketing or benchmarking studies. The patent intelligence clients are usually patent lawyers or intellectual property groups within manufacturing companies.
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© 2007 Tom Cheyney
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